Patents by Inventor Jeffrey A. West

Jeffrey A. West has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210305178
    Abstract: An electronic device comprises a multilevel metallization structure over a semiconductor layer and including a first region, a second region, a pre-metal level on the semiconductor layer, and N metallization structure levels over the pre-metal level, N being greater than 3. The electronic device also comprises an isolation component in the first region, the isolation component including a first terminal and a second terminal in different respective metallization structure levels, as well as a conductive shield between the first region and the second region in the multilevel metallization structure, the conductive shield including interconnected metal lines and trench vias in the respective metallization structure levels that at least partially encircle the first region.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Applicant: Texas Instruments Incorporated
    Inventor: Jeffrey A. West
  • Publication number: 20210280533
    Abstract: An integrated circuit (IC) includes a substrate having functional circuitry for realizing at least one circuit function configured together with at least one high voltage isolation component including a top metal feature above the substrate. A crack suppressing dielectric structure including at least a crack resistant dielectric layer is on at least a top of the top metal feature. At least one dielectric passivation overcoat (PO) layer is on an outer portion of the top metal feature.
    Type: Application
    Filed: May 25, 2021
    Publication date: September 9, 2021
    Inventors: ELIZABETH COSTNER STEWART, JEFFREY A. WEST
  • Patent number: 11100594
    Abstract: A method for correlating energy usage data and water usage data to a waste scoring system is described. In one embodiment, the method includes receiving energy usage data and water usage data from a plurality of users, identifying at least one user group from the plurality of users based on predetermined parameters, and calculating average energy usage and average water usage for each of the user groups. The energy usage data and water usage data received for an individual user may then be compared to the calculated average energy usage and calculated average water usage for at least one of the user groups, and a general waste score may be calculated for the individual user. In some cases, a plurality of sub-waste scores may be calculated indicating factors of energy usage and factors of water usage for the individual user.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: August 24, 2021
    Assignee: Vivint, Inc.
    Inventors: Dallin West, Jeffrey David Whitlock, Ryan Beck
  • Patent number: 11087451
    Abstract: A method comprises obtaining a wafer comprising a plurality of components, wherein each of the plurality of components exposes a first surface of the component present in a first focal plane and a second surface of the component present in a second focal plane. The method comprises generating, by an optical tool, a first image of the first surface and a second image of the second surface of one of the plurality of components. The method comprises comparing, by a processor, the first image with a first reference image to produce a first value and the second image with a second reference image to produce a second value. The method comprises generating, by the processor, a wafer map indicating a quality state of the one of the plurality of components based on the first and second values.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 10, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Elizabeth C. Stewart, Young Sawk Oh, Zhiyi Yu, Jeffrey A. West, Thomas D. Bonifield
  • Patent number: 11069627
    Abstract: A semiconductor die includes a plurality of layers, the plurality of layers having a top surface. A scribe seal is located in the plurality of layers and includes a first metal stack having a first metal layer located proximate the top surface. A trench is located in at least one layer of the plurality of layers. The trench extends from the top surface of the plurality of layers and is located a distance from the first metal stack. An electrical insulating layer is located on the top surface. The electrical insulating layer covers at least a portion of the top surface adjacent the first metal layer and extends a distance from the top surface of the first metal layer.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: July 20, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas D. Bonifield, Jeffrey A. West, Byron Williams, Honglin Guo
  • Patent number: 11049820
    Abstract: An integrated circuit (IC) includes a substrate having functional circuitry for realizing at least one circuit function configured together with at least one high voltage isolation component including a top metal feature above the substrate. A crack suppressing dielectric structure including at least a crack resistant dielectric layer is on at least a top of the top metal feature. At least one dielectric passivation overcoat (PO) layer is on an outer portion of the top metal feature.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: June 29, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Elizabeth Costner Stewart, Jeffrey A. West
  • Publication number: 20210143249
    Abstract: An integrated capacitor on a semiconductor surface on a substrate includes a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate. The capacitor dielectric layer includes a pitted sloped dielectric sidewall. Each of the pits is at least partially filled by one of a plurality of noncontiguous dielectric portions. A conformal dielectric layer may be formed over the noncontiguous dielectric portions. A top metal layer provides a top plate of the capacitor.
    Type: Application
    Filed: January 25, 2021
    Publication date: May 13, 2021
    Inventors: ELIZABETH COSTNER STEWART, JEFFREY A. WEST, THOMAS D. BONIFIELD, JOSEPH ANDRE GALLEGOS, JAY SUNG CHUN, ZHIYI YU
  • Patent number: 10978548
    Abstract: A method of forming an integrated capacitor on a semiconductor surface on a substrate includes etching a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate which is above and electrically isolated from the semiconductor surface to provide at least one defined dielectric feature having sloped dielectric sidewall portion. A dielectric layer is deposited to at least partially fill pits in the sloped dielectric sidewall portion to smooth a surface of the sloped dielectric sidewall portion. The dielectric layer is etched, and a top plate is then formed on top of the dielectric feature.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: April 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Elizabeth Costner Stewart, Jeffrey A. West, Thomas D. Bonifield, Joseph Andre Gallegos, Jay Sung Chun, Zhiyi Yu
  • Patent number: 10679935
    Abstract: A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A first dielectric layer has a first dielectric constant located over a semiconductor substrate. A metal structure located over the first dielectric layer has a side surface. A second dielectric layer having a second different dielectric constant is located adjacent the metal structure. A dielectric structure located between the side surface of the metal structure and the second dielectric layer has the first dielectric constant.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: June 9, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. West, Byron Lovell Williams, David Leonard Larkin, Weidong Tian
  • Patent number: 10665543
    Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: May 26, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. West, Kezhakkedath R. Udayakumar, Eric H. Warninghoff, Alan G. Merriam, Rick A. Faust
  • Publication number: 20200085819
    Abstract: Methods for treating Down syndrome and improving cognitive function of a patient with an intellectual disability are disclosed. 5-hydroxytryptamine sub-receptor six (5-HT6) receptor antagonists are provided for improving the cognition of a Down syndrome patient.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 19, 2020
    Applicant: THE UNIVERSITY OF UTAH RESEARCH FOUNDATION
    Inventors: Julie Ruth Korenberg, Karen Sue Wilcox, Peter Jeffrey West, Raymond Pierre Kesner
  • Publication number: 20200035617
    Abstract: An integrated circuit (IC) includes a substrate having functional circuitry for realizing at least one circuit function configured together with at least one high voltage isolation component including a top metal feature above the substrate. A crack suppressing dielectric structure including at least a crack resistant dielectric layer is on at least a top of the top metal feature. At least one dielectric passivation overcoat (PO) layer is on an outer portion of the top metal feature.
    Type: Application
    Filed: July 30, 2018
    Publication date: January 30, 2020
    Inventors: ELIZABETH COSTNER STEWART, JEFFREY A. WEST
  • Publication number: 20200013713
    Abstract: A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A first dielectric layer has a first dielectric constant located over a semiconductor substrate. A metal structure located over the first dielectric layer has a side surface. A second dielectric layer having a second different dielectric constant is located adjacent the metal structure. A dielectric structure located between the side surface of the metal structure and the second dielectric layer has the first dielectric constant.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Inventors: Jeffrey A. West, Byron Lovell Williams, David Leonard Larkin, Weidong Tian
  • Publication number: 20190378892
    Abstract: An electronic device, e.g. integrated circuit, has top and bottom metal plates located over a substrate, the bottom plate located between the top plate and the substrate. A high-stress silicon dioxide layer is located between the bottom plate and the substrate. At least one low-stress silicon dioxide layer is located between the top plate and the bottom plate.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 12, 2019
    Inventors: Elizabeth Costner Stewart, Jeffrey A. West, Thomas D. Bonifield
  • Patent number: 10478436
    Abstract: Methods for treating Down syndrome and improving cognitive function of a patient with an intellectual disability are disclosed. 5-hydroxytryptamine sub-receptor six (5-HT6) receptor antagonists are provided for improving the cognition of a Down syndrome patient.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: November 19, 2019
    Assignee: THE UNIVERSITY OF UTAH RESEARCH FOUNDATION
    Inventors: Julie Ruth Korenberg, Karen Sue Wilcox, Peter Jeffrey West, Raymond Pierre Kesner
  • Patent number: 10418320
    Abstract: A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A metal plate having a top surface and a side surface is located over a first dielectric layer. A second dielectric layer of a second different material is located over the first metal plate. A dielectric structure of the first material is located over the side surface of the metal plate and over the surface of the first dielectric layer.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: September 17, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. West, Byron Lovell Williams, David Leonard Larkin, Weidong Tian
  • Publication number: 20190188839
    Abstract: A method comprises obtaining a wafer comprising a plurality of components, wherein each of the plurality of components exposes a first surface of the component present in a first focal plane and a second surface of the component present in a second focal plane. The method comprises generating, by an optical tool, a first image of the first surface and a second image of the second surface of one of the plurality of components. The method comprises comparing, by a processor, the first image with a first reference image to produce a first value and the second image with a second reference image to produce a second value. The method comprises generating, by the processor, a wafer map indicating a quality state of the one of the plurality of components based on the first and second values.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 20, 2019
    Inventors: Elizabeth C. STEWART, Young Sawk OH, Zhiyi YU, Jeffrey A. WEST, Thomas D. BONIFIELD
  • Publication number: 20190006276
    Abstract: A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A metal plate having a top surface and a side surface is located over a first dielectric layer. A second dielectric layer of a second different material is located over the first metal plate. A dielectric structure of the first material is located over the side surface of the metal plate and over the surface of the first dielectric layer.
    Type: Application
    Filed: September 11, 2018
    Publication date: January 3, 2019
    Inventors: Jeffrey A. West, Byron Lovell Williams, David Leonard Larkin, Weidong Tian
  • Patent number: 10122650
    Abstract: In accordance with an embodiment, described herein is a system and method for providing tenant management in a cloud computing environment. In accordance with an embodiment, a tenant manager component enables configuration and management of tenants that utilize services and resources within the cloud environment, including accessing information in a tenant store repository describing a plurality of tenants, and providing administrative isolation between the plurality of tenants. The tenant manager enables receiving administrative commands to configure or manage particular ones of the plurality of tenants, and applying the administrative commands to the particular tenants associated with the received administrative commands, for use in configuring or managing use by those tenants of the services and resources within the cloud environment.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: November 6, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Mitesh Meswani, Nazrul Islam, Rajiv Mordani, Jeffrey West, Andriy Zhdanov
  • Publication number: 20180308802
    Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.
    Type: Application
    Filed: June 18, 2018
    Publication date: October 25, 2018
    Inventors: Jeffrey A. West, Kezhakkedath R. Udayakumar, Eric H. Warninghoff, Alan G. Merriam, Rick A. Faust