Patents by Inventor Jeffrey H. Derby
Jeffrey H. Derby has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11119766Abstract: Provided are techniques for a hardware accelerator with locally stored macros. A plurality of macros are stored in a lookup memory of a hardware accelerator. In response to receiving an operation code, the operation code is mapped to one or more macros of the plurality of macros, wherein each of the one or more macros includes micro-instructions. Each of the micro-instructions of the one or more macros is routed to a function block of a plurality of function blocks. Each of the micro-instructions is processed with the plurality of function blocks. Data from the processing of each of the micro-instructions is stored in an accelerator memory of the hardware accelerator. The data is moved from the accelerator memory to a host memory.Type: GrantFiled: December 6, 2018Date of Patent: September 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael J. Healy, Jason A. Viehland, Jeffrey H. Derby, Diana L. Orf
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Patent number: 11061675Abstract: Systems and methods are provided for executing an instruction. The method may include loading a first vector into a first location, the first vector including a plurality of first data elements and loading a second vector into a second location, the second vector including a plurality of second data elements. The method may further include comparing the plurality of first data elements of the first vector to the plurality of data elements of the second vector and performing one or more operations on the plurality of first and second data elements based on at least one vector cross-compare instruction. The one or more operations include counting a number of data elements of the plurality of first and second data elements that satisfy at least one condition, counting a number of times specified values occur in the plurality of first and second data elements, and generating sequence counts for duplicated values.Type: GrantFiled: October 25, 2019Date of Patent: July 13, 2021Assignee: International Business Machines CorporationInventors: Jeffrey H. Derby, Robert K. Montoye, Dheeraj Sreedhar
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Publication number: 20200183686Abstract: Provided are techniques for a hardware accelerator with locally stored macros. A plurality of macros are stored in a lookup memory of a hardware accelerator. In response to receiving an operation code, the operation code is mapped to one or more macros of the plurality of macros, wherein each of the one or more macros includes micro-instructions. Each of the micro-instructions of the one or more macros is routed to a function block of a plurality of function blocks. Each of the micro-instructions is processed with the plurality of function blocks. Data from the processing of each of the micro-instructions is stored in an accelerator memory of the hardware accelerator. The data is moved from the accelerator memory to a host memory.Type: ApplicationFiled: December 6, 2018Publication date: June 11, 2020Inventors: Michael J. Healy, Jason A. Viehland, Jeffrey H. Derby, Diana L. Orf
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Publication number: 20200057637Abstract: Systems and methods are provided for executing an instruction. The method may include loading a first vector into a first location, the first vector including a plurality of first data elements and loading a second vector into a second location, the second vector including a plurality of second data elements. The method may further include comparing the plurality of first data elements of the first vector to the plurality of data elements of the second vector and performing one or more operations on the plurality of first and second data elements based on at least one vector cross-compare instruction. The one or more operations include counting a number of data elements of the plurality of first and second data elements that satisfy at least one condition, counting a number of times specified values occur in the plurality of first and second data elements, and generating sequence counts for duplicated values.Type: ApplicationFiled: October 25, 2019Publication date: February 20, 2020Inventors: Jeffrey H. Derby, Robert K. Montoye, Dheeraj Sreedhar
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Patent number: 10564964Abstract: Systems and methods are provided for executing an instruction. The method may include loading a first vector into a first location, the first vector including a plurality of first data elements and loading a second vector into a second location, the second vector including a plurality of second data elements. The method may further include comparing the plurality of first data elements of the first vector to the plurality of data elements of the second vector and performing one or more operations on the plurality of first and second data elements based on at least one vector cross-compare instruction. The one or more operations include counting a number of data elements of the plurality of first and second data elements that satisfy at least one condition, counting a number of times specified values occur in the plurality of first and second data elements, and generating sequence counts for duplicated values.Type: GrantFiled: August 23, 2016Date of Patent: February 18, 2020Assignee: International Business Machines CorporationInventors: Jeffrey H. Derby, Robert K. Montoye, Dheeraj Sreedhar
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Patent number: 10248419Abstract: Methods, systems and computer program products for accelerating sorting of data are provided herein. A computer-implemented method includes retrieving a plurality of cache lines of data from an input buffer, wherein each cache line comprises a plurality of elements, scattering the plurality of elements of each retrieved cache line into a plurality of bins, wherein said scattering comprises using one or more vector instructions, forming a bin cache line in a corresponding one of the plurality of bins, wherein the bin cache line comprises a group of the plurality of elements which were scattered to the corresponding one of the plurality of bins, writing the bin cache line from the corresponding one of the plurality of bins to a memory, and loading the bin cache line from the memory to the input buffer.Type: GrantFiled: March 9, 2016Date of Patent: April 2, 2019Assignee: International Business Machines CorporationInventors: Jeffrey H. Derby, Robert Montoye, Dheeraj Sreedhar
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Patent number: 10042876Abstract: Methods and arrangements for joining data sets. There are accepted: a first data set which forms a table in a relational database, and a second data set which forms a table in a relational database, each of the first and second data sets comprising a key value. Each of the first and second data sets is hashed based on the key value, and are thereupon sorted based on the key value. The sorted first and second data sets are joined with one another based on the key value. Other variants and embodiments are broadly contemplated herein.Type: GrantFiled: September 17, 2014Date of Patent: August 7, 2018Assignee: International Business Machines CorporationInventors: Jeffrey H. Derby, Robert Kevin Montoye, Dheeraj Sreedhar
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Publication number: 20180060072Abstract: Systems and methods are provided for executing an instruction. The method may include loading a first vector into a first location, the first vector including a plurality of first data elements and loading a second vector into a second location, the second vector including a plurality of second data elements. The method may further include comparing the plurality of first data elements of the first vector to the plurality of data elements of the second vector and performing one or more operations on the plurality of first and second data elements based on at least one vector cross-compare instruction. The one or more operations include counting a number of data elements of the plurality of first and second data elements that satisfy at least one condition, counting a number of times specified values occur in the plurality of first and second data elements, and generating sequence counts for duplicated values.Type: ApplicationFiled: August 23, 2016Publication date: March 1, 2018Inventors: Jeffrey H. Derby, Robert K. Montoye, Dheeraj Sreedhar
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Patent number: 9817612Abstract: In one embodiment, a computer-implemented method includes issuing, to a DRAM with EIP, a first group of two or more load requests to load data from a hash table constructed from hashed join-key values of a dimension table for a hash-join procedure. A second group of two or more load requests is issued. First response data is received, responsive to the first group of load requests. The first response data is processed while awaiting second response data responsive to the second group. Processing the first response data includes identifying matches between the join-key values corresponding to entries in the load requests of the first group and one or more hash buckets in the first response data. The size of the second group of load requests is selected such that a time for processing the first response data is approximately equal to the latency in receiving the second response data.Type: GrantFiled: December 30, 2014Date of Patent: November 14, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey H. Derby, Charles Johnson, Robert K. Montoye, Dheeraj Sreedhar, Steven P. VanderWiel
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Patent number: 9811287Abstract: In one embodiment, a computer-implemented method includes issuing, to a DRAM with EIP, a first group of two or more load requests to load data from a hash table constructed from hashed join-key values of a dimension table for a hash-join procedure. A second group of two or more load requests is issued. First response data is received, responsive to the first group of load requests. The first response data is processed while awaiting second response data responsive to the second group. Processing the first response data includes identifying matches between the join-key values corresponding to entries in the load requests of the first group and one or more hash buckets in the first response data. The size of the second group of load requests is selected such that a time for processing the first response data is approximately equal to the latency in receiving the second response data.Type: GrantFiled: June 25, 2015Date of Patent: November 7, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey H. Derby, Charles L. Johnson, Robert K. Montoye, Dheeraj Sreedhar, Steven P. VanderWiel
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Publication number: 20170262211Abstract: Methods, systems and computer program products for accelerating sorting of data are provided herein. A computer-implemented method includes retrieving a plurality of cache lines of data from an input buffer, wherein each cache line comprises a plurality of elements, scattering the plurality of elements of each retrieved cache line into a plurality of bins, wherein said scattering comprises using one or more vector instructions, forming a bin cache line in a corresponding one of the plurality of bins, wherein the bin cache line comprises a group of the plurality of elements which were scattered to the corresponding one of the plurality of bins, writing the bin cache line from the corresponding one of the plurality of bins to a memory, and loading the bin cache line from the memory to the input buffer.Type: ApplicationFiled: March 9, 2016Publication date: September 14, 2017Inventors: Jeffrey H. Derby, Robert Montoye, Dheeraj Sreedhar
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Patent number: 9740659Abstract: Methods, systems, and articles of manufacture for merging and sorting arrays on a processor are provided herein. A method includes splitting an input array into multiple sub-arrays across multiple processing elements; merging the multiple sub-arrays into multiple vectors; and sorting the multiple vectors by comparing and swapping one or more vector elements among the multiple vectors.Type: GrantFiled: March 19, 2014Date of Patent: August 22, 2017Assignee: International Business Machines CorporationInventors: Dheeraj Sreedhar, Robert Montoye, Jeffrey H. Derby
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Patent number: 9710310Abstract: A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.Type: GrantFiled: August 17, 2015Date of Patent: July 18, 2017Assignee: International Business Machines CorporationInventors: Brian M. Bass, Bartholomew Blaner, George W. Daly, Jr., Jeffrey H. Derby, Ross B. Leavens, Joseph G. McDonald
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Patent number: 9606838Abstract: A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.Type: GrantFiled: August 17, 2015Date of Patent: March 28, 2017Assignee: International Business Machines CorporationInventors: Brian M. Bass, Bartholomew Blaner, George W. Daly, Jr., Jeffrey H. Derby, Ross B. Leavens, Joseph G. McDonald
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Patent number: 9584178Abstract: In one embodiment, a method includes receiving a signal having communication data from two or more mobile devices, each identifiable by an associated pseudonoise sequence. A first mobile device is identifiable by a first pseudonoise sequence. Two or more samples of the received signal are stored in an input register. A segment of the first pseudonoise sequence is stored as a bit vector in a second register. The SIMD instruction is processed, by an SIMD processor, to produce correlation values associated with the segment of the first pseudonoise sequence and the samples of the received signal. Processing the SIMD instruction includes distributing the segment of the first pseudonoise sequence, as a bit vector, across two or more lanes of the SIMD processor. The processing contributes to despreading the received signal, and an output of the processing includes at least a portion of the communication data from the first mobile device.Type: GrantFiled: July 21, 2014Date of Patent: February 28, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey H. Derby, Dheeraj Sreedhar
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Publication number: 20160147450Abstract: In one embodiment, a computer-implemented method includes issuing, to a DRAM with EIP, a first group of two or more load requests to load data from a hash table constructed from hashed join-key values of a dimension table for a hash-join procedure. A second group of two or more load requests is issued. First response data is received, responsive to the first group of load requests. The first response data is processed while awaiting second response data responsive to the second group. Processing the first response data includes identifying matches between the join-key values corresponding to entries in the load requests of the first group and one or more hash buckets in the first response data. The size of the second group of load requests is selected such that a time for processing the first response data is approximately equal to the latency in receiving the second response data.Type: ApplicationFiled: December 30, 2014Publication date: May 26, 2016Inventors: Jeffrey H. Derby, Charles Johnson, Robert K. Montoye, Dheeraj Sreedhar, Steven P. VanderWiel
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Publication number: 20160147451Abstract: In one embodiment, a computer-implemented method includes issuing, to a DRAM with EIP, a first group of two or more load requests to load data from a hash table constructed from hashed join-key values of a dimension table for a hash-join procedure. A second group of two or more load requests is issued. First response data is received, responsive to the first group of load requests. The first response data is processed while awaiting second response data responsive to the second group. Processing the first response data includes identifying matches between the join-key values corresponding to entries in the load requests of the first group and one or more hash buckets in the first response data. The size of the second group of load requests is selected such that a time for processing the first response data is approximately equal to the latency in receiving the second response data.Type: ApplicationFiled: June 25, 2015Publication date: May 26, 2016Inventors: Jeffrey H. Derby, Charles L. Johnson, Robert K. Montoye, Dheeraj Sreedhar, Steven P. VanderWiel
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Publication number: 20160078031Abstract: Methods and arrangements for joining data sets. There are accepted: a first data set which forms a table in a relational database, and a second data set which forms a table in a relational database, each of the first and second data sets comprising a key value. Each of the first and second data sets is hashed based on the key value, and are thereupon sorted based on the key value. The sorted first and second data sets are joined with one another based on the key value. Other variants and embodiments are broadly contemplated herein.Type: ApplicationFiled: September 17, 2014Publication date: March 17, 2016Inventors: Jeffrey H. Derby, Robert Kevin Montoye, Dheeraj Sreedhar
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Publication number: 20160020821Abstract: In one embodiment, a method includes receiving a signal having communication data from two or more mobile devices, each identifiable by an associated pseudonoise sequence. A first mobile device is identifiable by a first pseudonoise sequence. Two or more samples of the received signal are stored in an input register. A segment of the first pseudonoise sequence is stored as a bit vector in a second register. The SIMD instruction is processed, by an SIMD processor, to produce correlation values associated with the segment of the first pseudonoise sequence and the samples of the received signal. Processing the SIMD instruction includes distributing the segment of the first pseudonoise sequence, as a bit vector, across two or more lanes of the SIMD processor. The processing contributes to despreading the received signal, and an output of the processing includes at least a portion of the communication data from the first mobile device.Type: ApplicationFiled: July 21, 2014Publication date: January 21, 2016Inventors: Jeffrey H. Derby, Dheeraj Sreedhar
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Publication number: 20150355948Abstract: A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.Type: ApplicationFiled: August 17, 2015Publication date: December 10, 2015Inventors: Brian M. Bass, Bartholomew Blaner, George W. Daly, Jr., Jeffrey H. Derby, Ross B. Leavens, Joseph G. McDonald