Patents by Inventor Jeffrey J. Irwin
Jeffrey J. Irwin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230353339Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.Type: ApplicationFiled: May 2, 2023Publication date: November 2, 2023Inventors: Christopher D. Finan, Alexander Ukanwa, Charles F. Dominguez, Jean-Didier Allegrucci, Jeffrey J. Irwin, Kalpana Bansal, Michael Bekerman, Remi Clavel
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Patent number: 11778211Abstract: Systems and methods of parallel image parsing and processing for video decoding are provided. Video decoder circuitry may enable an incoming encoded bitstream to be split into multiple bitstreams corresponding to the bitstream compression scheme and processed by multiple parsers corresponding to the bitstream compression scheme in parallel. This enables parallel decoding of the incoming bitstream and, thus, more efficient decoder processing.Type: GrantFiled: September 16, 2021Date of Patent: October 3, 2023Assignee: Apple Inc.Inventors: Yaxiong Zhou, Felix C. Fernandes, Jeffrey J. Irwin, Liviu R. Morogan, Sorin Constantin Cismas
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Patent number: 11683149Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.Type: GrantFiled: September 10, 2021Date of Patent: June 20, 2023Assignee: Apple Inc.Inventors: Christopher D. Finan, Alexander Ukanwa, Charles F. Dominguez, Jean-Didier Allegrucci, Jeffrey J. Irwin, Kalpana Bansal, Michael Bekerman, Remi Clavel
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Publication number: 20230081975Abstract: Systems and methods of parallel image parsing and processing for video decoding are provided. Video decoder circuitry may enable an incoming encoded bitstream to be split into multiple bitstreams corresponding to the bitstream compression scheme and processed by multiple parsers corresponding to the bitstream compression scheme in parallel. This enables parallel decoding of the incoming bitstream and, thus, more efficient decoder processing.Type: ApplicationFiled: September 16, 2021Publication date: March 16, 2023Inventors: Yaxiong Zhou, Felix C. Fernandes, Jeffrey J. Irwin, Liviu R. Morogan, Sorin Constantin Cismas
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Publication number: 20220085969Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.Type: ApplicationFiled: September 10, 2021Publication date: March 17, 2022Inventors: Christopher D. Finan, Alexander Ukanwa, Charles F. Dominguez, Jean-Didier Allegrucci, Jeffrey J. Irwin, Kalpana Bansal, Michael Bekerman, Remi Clavel
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Patent number: 10546558Abstract: Systems, apparatuses, and methods for aggregating memory requests with opportunism in a display pipeline. Memory requests are aggregated for each requestor of a plurality of requestors in the display pipeline. When the number of memory requests for a given requestor reaches a corresponding threshold, memory requests may be issued for the given requestor. In response to determining the given requestor has reached its threshold, other requestors may issue memory requests even if they have not yet aggregated enough memory requests to reach their corresponding thresholds.Type: GrantFiled: April 25, 2014Date of Patent: January 28, 2020Assignee: Apple Inc.Inventors: Marc A. Schaub, Jeffrey J. Irwin, Peter F. Holland
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Patent number: 9412147Abstract: An apparatus for processing graphics data may include a plurality of processing pipelines, each pipeline configured to receive and process pixel data. A functional unit may combine the outputs of each processing pipeline. A buffer included in a given processing pipeline may be configured to store data from the functional unit in response to a determination that the given processing pipeline is inactive. The buffer may then send the stored data to a memory.Type: GrantFiled: September 23, 2014Date of Patent: August 9, 2016Assignee: Apple Inc.Inventors: Peter F. Holland, Hari Ganesh R. Thirunageswaram, Jeffrey J. Irwin
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Publication number: 20160086298Abstract: An apparatus for processing graphics data may include a plurality of processing pipelines, each pipeline configured to receive and process pixel data. A functional unit may combine the outputs of each processing pipeline. A buffer included in a given processing pipeline may be configured to store data from the functional unit in response to a determination that the given processing pipeline is inactive. The buffer may then send the stored data to a memory.Type: ApplicationFiled: September 23, 2014Publication date: March 24, 2016Inventors: Peter F. Holland, Hari Ganesh R. Thirunageswaram, Jeffrey J. Irwin
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Publication number: 20150310900Abstract: Systems, apparatuses, and methods for aggregating memory requests with opportunism in a display pipeline. Memory requests are aggregated for each requestor of a plurality of requestors in the display pipeline. When the number of memory requests for a given requestor reaches a corresponding threshold, memory requests may be issued for the given requestor. In response to determining the given requestor has reached its threshold, other requestors may issue memory requests even if they have not yet aggregated enough memory requests to reach their corresponding thresholds.Type: ApplicationFiled: April 25, 2014Publication date: October 29, 2015Applicant: Apple Inc.Inventors: Marc A. Schaub, Jeffrey J. Irwin, Peter F. Holland
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Patent number: 9164766Abstract: Methods and apparatus for providing additional storage, in the form of a hardware assisted stack, usable by software running an environment with limited resources. As an example, the hardware assisted stack may provide additional stack space to VBIOS code that is accessible within its limited allocated address space.Type: GrantFiled: April 8, 2005Date of Patent: October 20, 2015Assignee: NVIDIA CorporationInventors: Aron L. Wong, Dennis K. Ma, Jonah M. Alben, Mark S. Krueger, Jeffrey J. Irwin
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Patent number: 7657775Abstract: Methods, circuits, and apparatus for changing a frequency of a clock signal provided to a graphics memory while reducing any resulting visual glitch or disturbance on a monitor. A specific embodiment provides multiple clock sources that may be multiplexed or selected to provide a memory clock signal to the graphics memory. The multiplexer switches from providing a first clock source signal as the memory clock signal to providing a second clock source signal as the memory clock signal. The first clock source changes its frequency of operation. After the first clock source settles or stabilizes, the multiplexer switches back to providing the first clock source signal as the memory clock signal.Type: GrantFiled: November 22, 2007Date of Patent: February 2, 2010Assignee: NVIDIA CorporationInventors: Barry Wagner, Jonah M. Alben, Sonny Yeoh, Jeffrey J. Irwin, Saurabh Gupta
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Patent number: 7315957Abstract: Methods, circuits, and apparatus for changing a frequency of a clock signal provided to a graphics memory while reducing any resulting visual glitch or disturbance on a monitor. A specific embodiment provides multiple clock sources that may be multiplexed or selected to provide a memory clock signal to the graphics memory. The multiplexer switches from providing a first clock source signal as the memory clock signal to providing a second clock source signal as the memory clock signal. The first clock source changes its frequency of operation. After the first clock source settles or stabilizes, the multiplexer switches back to providing the first clock source signal as the memory clock signal.Type: GrantFiled: December 18, 2003Date of Patent: January 1, 2008Assignee: NVIDIA CorporationInventors: Barry Wagner, Jonah M. Alben, Sonny Yeoh, Jeffrey J. Irwin, Saurabh Gupta
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Patent number: 7068278Abstract: A graphics processing unit, which includes a clock generator configured to generate a clock signal and a controller coupled to the clock generator. The controller is configured to receive the clock signal, compare the clock signal with a synchronization signal to generate a timing signal, and transmit the timing signal to a second graphics processing unit connected to the graphics processing unit.Type: GrantFiled: December 11, 2003Date of Patent: June 27, 2006Assignee: NVIDIA CorporationInventors: Ian M. Williams, Dale Ah Tye, Jeffrey J. Irwin, John S. Montrym, Michael Diamond