Patents by Inventor Jeffrey Michael Dodson
Jeffrey Michael Dodson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10073805Abstract: Methods and structure for utilizing a virtual Expansion ROM. One exemplary embodiment is a management device. The management device includes a memory, a Peripheral Component Interconnect Express (PCIe) link, and a processor. The memory stores Expansion Read-Only Memory (Expansion ROM) boot instructions for a host. The processor identifies devices in a PCIe hierarchy by transmitting PCIe enumeration requests via the PCIe link. The processor also generates a synthetic PCIe hierarchy that includes an added virtual Expansion ROM which is not present in the PCIe hierarchy, and provides responses describing the synthetic PCIe hierarchy to a host. Furthermore, the processor acquires PCIe read requests initiated by the host that are directed to the virtual Expansion ROM, and provides boot instructions to the host from the memory based on the PCIe read requests.Type: GrantFiled: September 3, 2015Date of Patent: September 11, 2018Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Rajendran Vishwanathan, Nagarajan Subramaniyan, Jeffrey Michael Dodson, Jack Regula
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Publication number: 20170068636Abstract: Methods and structure for utilizing a virtual Expansion ROM. One exemplary embodiment is a management device. The management device includes a memory, a Peripheral Component Interconnect Express (PCIe) link, and a processor. The memory stores Expansion Read-Only Memory (Expansion ROM) boot instructions for a host. The processor identifies devices in a PCIe hierarchy by transmitting PCIe enumeration requests via the PCIe link. The processor also generates a synthetic PCIe hierarchy that includes an added virtual Expansion ROM which is not present in the PCIe hierarchy, and provides responses describing the synthetic PCIe hierarchy to a host. Furthermore, the processor acquires PCIe read requests initiated by the host that are directed to the virtual Expansion ROM, and provides boot instructions to the host from the memory based on the PCIe read requests.Type: ApplicationFiled: September 3, 2015Publication date: March 9, 2017Inventors: Rajendran Vishwanathan, Nagarajan Subramaniyan, Jeffrey Michael Dodson, Jack Regula
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Publication number: 20160154756Abstract: A method of providing unordered packet routing in a multi-path PCIe switch fabric is provided. Fabric egress port congestion is measured and distributed to all ports within a switch and to neighboring switches. An unordered route choice vector is generated by table lookup. The local congestion mask vector identifies which of these choices has local congestion. A next hop masked choice vector generated by table lookup is gated with the next hop congestion mask vectors, received from neighboring switches, to identify the choices that have next hop congestion. Congested choices are excluded by masking. If multiple choices remain at the conclusion of the masking process, then a selection is made by round-robin among the surviving choices. If no choices remain, the selection is made by round robin among the original choices. The final selection is mapped to an egress port on the switch by table lookup.Type: ApplicationFiled: December 2, 2014Publication date: June 2, 2016Inventors: Jeffrey Michael DODSON, Jack REGULA, Natwar AGRAWAL
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Patent number: 9223734Abstract: A method of sharing of a function of a device with a plurality of hosts through a PCIe switch is provided. A function on a device is presented to a first host and a second host through the switch. Read and write on the function's register set within the first host and within the second host are captured, thereby enabling a management system of the switch to create a shadow copy of the first host register sets and second host register sets. The creation of sets of shadow queues on the management system is enabled. The first set of shadow queues of the first set of registers is used to direct read and write operations from the first host to the function. The second set of shadow queues of the second set of registers is used to direct read and write operations from the second host to the function.Type: GrantFiled: December 13, 2013Date of Patent: December 29, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Nagarajan Subramaniyan, Jeffrey Michael Dodson, Jack Regula
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Patent number: 9141571Abstract: A PCIe switch implements a logical device for use by connected host systems. The logical device is created by logical device enabling software running on a host management system. The logical device is able to consolidate one or more physical devices or may be entirely software-based. Commands from the connected host are processed in the command and response queues in the host and are also reflected in shadow queues stored in the management system. A DMA engine associated with the connected host is set up to automatically trigger on queues in the connected (local) host. Commands are sent to the physical devices to complete the work and a completion signal is sent to the management software and a response to the work is sent directly to the connected host, which is not aware that the logical device is non-existent and is implemented by software in the management system.Type: GrantFiled: September 21, 2012Date of Patent: September 22, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Nagarajan Subramaniyan, Jack Regula, Jeffrey Michael Dodson
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Publication number: 20150169487Abstract: A method of sharing of a function of a device with a plurality of hosts through a PCIe switch is provided. A function on a device is presented to a first host and a second host through the switch. Read and write on the function's register set within the first host and within the second host are captured, thereby enabling a management system of the switch to create a shadow copy of the first host register sets and second host register sets. The creation of sets of shadow queues on the management system is enabled. The first set of shadow queues of the first set of registers is used to direct read and write operations from the first host to the function. The second set of shadow queues of the second set of registers is used to direct read and write operations from the second host to the function.Type: ApplicationFiled: December 13, 2013Publication date: June 18, 2015Inventors: Nagarajan SUBRAMANIYAN, Jeffrey Michael DODSON, Jack REGULA
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Patent number: 8880771Abstract: A PCIe fabric includes at least one PCIe switch. The fabric may be used to connect multiple hosts. The PCIe switch implements security and segregation measures for host-to-host message communication. A management entity defines a Virtual PCIe Fabric ID (VPFID). The VPFID is used to enforce security and segregation. The fabric ID may be extended to be used in switch fabrics with other point-to-point protocols.Type: GrantFiled: October 25, 2012Date of Patent: November 4, 2014Assignee: PLX Technology, Inc.Inventors: Nagarajan Subramaniyan, Jack Regula, Jeffrey Michael Dodson
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Patent number: 8797857Abstract: In a first embodiment of the present invention, a method for handling a Transaction Layer Packets (TLPs) from devices in a switch is provided, the method comprising: subtracting a first number of credits from a credit pool associated with a first port on which a first device is connected; determining if the amount of credits in the credit pool associated with the first port is less than a first predetermined threshold; and if the amount of credits in the credit pool associated with the first port is less than the first predetermined threshold, assigning a second number of credits from a shared credit pool to the credit pool associated with the first port.Type: GrantFiled: November 30, 2010Date of Patent: August 5, 2014Assignee: PLX Technology, Inc.Inventors: Jeffrey Michael Dodson, Joe Keirouz
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Publication number: 20140122765Abstract: A PCIe fabric includes at least one PCIe switch. The fabric may be used to connect multiple hosts. The PCIe switch implements security and segregation measures for host-to-host message communication. A management entity defines a Virtual PCIe Fabric ID (VPFID). The VPFID is used to enforce security and segregation. The fabric ID may be extended to be used in switch fabrics with other point-to-point protocols.Type: ApplicationFiled: October 25, 2012Publication date: May 1, 2014Applicant: PLX TECHNOLOGY, INC.Inventors: Nagarajan SUBRAMANIYAN, Jack REGULA, Jeffrey Michael DODSON
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Patent number: 8645605Abstract: A method is provided comprising: enumerating a group of available virtual functions corresponding to the physical function; mapping the group of available virtual functions to a non-transparent port of the switch by creating a copy of a configuration space for the physical function while assigning unique vendor and device identifications for different classes of devices, wherein the mapping creates a pseudo physical function exposing a subset of the SR-IOV capability from the configuration space for the physical function; receiving a request to access the physical function from the single host; and providing the pseudo physical function to the single host for loading on the single host, in response to the receiving of the request, wherein the pseudo physical function is designed to call management functions of the single host to enable the group of available virtual functions in a local hierarchy of the single host.Type: GrantFiled: August 18, 2011Date of Patent: February 4, 2014Assignee: PLX Technology, Inc.Inventors: Nagarajan Subramaniyan, Jack Regula, Jeffrey Michael Dodson
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Patent number: 8543890Abstract: In a first embodiment of the present invention, a method for operating a midpoint device utilizing an Input/Output (I/O) interconnect is provided, wherein the midpoint device contains a plurality of ports, the method comprising: receiving a request to initiate a session between a device on a first port of the midpoint device and a device on a second port of the midpoint device; retrieving information regarding whether the first port supports a feature, and information regarding whether the second port supports the feature; and when the first port supports the feature and the second port does not support the feature, permitting the session to be initiated, such that communications between the first device and the second device are performed partially using the feature, independently of support of the feature on other ports.Type: GrantFiled: April 26, 2012Date of Patent: September 24, 2013Assignee: PLX Technology, Inc.Inventor: Jeffrey Michael Dodson
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Publication number: 20120215948Abstract: In a first embodiment of the present invention, a method for operating a midpoint device utilizing an Input/Output (I/O) interconnect is provided, wherein the midpoint device contains a plurality of ports, the method comprising: receiving a request to initiate a session between a device on a first port of the midpoint device and a device on a second port of the midpoint device; retrieving information regarding whether the first port supports a feature, and information regarding whether the second port supports the feature; and when the first port supports the feature and the second port does not support the feature, permitting the session to be initiated, such that communications between the first device and the second device are performed partially using the feature, independently of support of the feature on other ports.Type: ApplicationFiled: April 26, 2012Publication date: August 23, 2012Applicant: PLX TECHNOLOGY, INC.Inventor: Jeffrey Michael DODSON
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Publication number: 20120167085Abstract: A method is provided comprising: enumerating a group of available virtual functions corresponding to the physical function; mapping the group of available virtual functions to a non-transparent port of the switch by creating a copy of a configuration space for the physical function while assigning unique vendor and device identifications for different classes of devices, wherein the mapping creates a pseudo physical function exposing a subset of the SR-IOV capability from the configuration space for the physical function; receiving a request to access the physical function from the single host; and providing the pseudo physical function to the single host for loading on the single host, in response to the receiving of the request, wherein the pseudo physical function is designed to call management functions of the single host to enable the group of available virtual functions in a local hierarchy of the single host.Type: ApplicationFiled: August 18, 2011Publication date: June 28, 2012Applicant: PLX TECHNOLOGY, INC.Inventors: Nagarajan SUBRAMANIYAN, Jack REGULA, Jeffrey Michael DODSON
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Patent number: 8196013Abstract: In a first embodiment of the present invention, a method for operating a midpoint device utilizing an Input/Output (I/O) interconnect is provided, wherein the midpoint device contains a plurality of ports, the method comprising: receiving a request to initiate a session between a device on a first port of the midpoint device and a device on a second port of the midpoint device; retrieving information regarding whether the first port supports a feature, and information regarding whether the second port supports the feature; and when the first port supports the feature and the second port does not support the feature, permitting the session to be initiated, such that communications between the first device and the second device are performed partially using the feature, independently of support of the feature on other ports.Type: GrantFiled: October 23, 2009Date of Patent: June 5, 2012Assignee: PLX Technology, Inc.Inventor: Jeffrey Michael Dodson
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Patent number: 8015330Abstract: In one embodiment, a method for controlling reads in a computer input/output (I/O) interconnect is provided. A read request is received over the computer I/O interconnect from a first device, the request requesting data of a first size. Then it is determined whether fulfilling the read request would cause the total size of a completion queue to exceed a first predefined threshold. If fulfilling the read request would cause the total size of the completion queue to exceed the first predefined threshold, then the read request is temporarily restricted from being forwarded upstream.Type: GrantFiled: February 3, 2011Date of Patent: September 6, 2011Assignee: PLX Technology, Inc.Inventors: Jeffrey Michael Dodson, Nagamanivel Balasubramaniyan
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Publication number: 20110153875Abstract: In a first embodiment of the present invention, a method for operating an I/O interconnect midpoint device is presented, wherein the midpoint device has a direct memory access (DMA) controller and a plurality of ports, the method comprising: generating, using the DMA controller, a DMA read request; sending, using the DMA controller, the DMA read request to a first device connected to a first of the plurality of ports; receiving data responsive to the DMA read request from the first device; generating, using the DMA controller, a DMA write request including the received data; and sending, using the DMA controller, the DMA write request to a second device connected to the second of the plurality of ports.Type: ApplicationFiled: December 18, 2009Publication date: June 23, 2011Applicant: PLX Technology, Inc.Inventors: Samir KHERICHA, Jeffrey Michael DODSON
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Publication number: 20110125947Abstract: In one embodiment, a method for controlling reads in a computer input/output (I/O) interconnect is provided. A read request is received over the computer I/O interconnect from a first device, the request requesting data of a first size. Then it is determined whether fulfilling the read request would cause the total size of a completion queue to exceed a first predefined threshold.Type: ApplicationFiled: February 3, 2011Publication date: May 26, 2011Applicant: PLX TECHNOLOGY, INC.Inventors: Jeffrey Michael DODSON, Nagamanivel BALASUBRAMANIYAN
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Publication number: 20110099456Abstract: In a first embodiment of the present invention, a method for operating a midpoint device utilizing an Input/Output (I/O) interconnect is provided, wherein the midpoint device contains a plurality of ports, the method comprising: receiving a request to initiate a session between a device on a first port of the midpoint device and a device on a second port of the midpoint device; retrieving information regarding whether the first port supports a feature, and information regarding whether the second port supports the feature; and when the first port supports the feature and the second port does not support the feature, permitting the session to be initiated, such that communications between the first device and the second device are performed partially using the feature, independently of support of the feature on other ports.Type: ApplicationFiled: October 23, 2009Publication date: April 28, 2011Applicant: PLX TECHNOLOGY, INC.Inventor: Jeffrey Michael DODSON
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Publication number: 20110069704Abstract: In a first embodiment of the present invention, a method for handling a Transaction Layer Packets (TLPs) from devices in a switch is provided, the method comprising: subtracting a first number of credits from a credit pool associated with a first port on which a first device is connected; determining if the amount of credits in the credit pool associated with the first port is less than a first predetermined threshold; and if the amount of credits in the credit pool associated with the first port is less than the first predetermined threshold, assigning a second number of credits from a shared credit pool to the credit pool associated with the first port.Type: ApplicationFiled: November 30, 2010Publication date: March 24, 2011Applicant: PLX Technology, Inc.Inventors: Jeffrey Michael DODSON, Joe KEIROUZ
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Patent number: 7869356Abstract: In a first embodiment of the present invention, a method for handling a Transaction Layer Packets (TLPs) from devices in a switch is provided, the method comprising: subtracting a first number of credits from a credit pool associated with a first port on which a first device is connected; determining if the amount of credits in the credit pool associated with the first port is less than a first predetermined threshold; and if the amount of credits in the credit pool associated with the first port is less than the first predetermined threshold, assigning a second number of credits from a shared credit pool to the credit pool associated with the first port.Type: GrantFiled: December 16, 2008Date of Patent: January 11, 2011Assignee: PLX Technology, Inc.Inventors: Jeffrey Michael Dodson, Joe Keirouz