Patents by Inventor Jeffrey P. Gambino

Jeffrey P. Gambino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BACKSIDE DEVICE CONTACT
    Publication number: 20180090432
    Abstract: A back-side device structure with a silicon-on-insulator substrate that includes: a first dielectric layer that includes a first via that communicates with a trench, a contact plug that fills the trench, and a first contact formed in a second dielectric layer. The first contact fills the first via and connects with the contact plug and a wire formed in a third dielectric layer. A final substrate is connected to a buried insulator layer of the silicon-on-insulator substrate such that the contact plug contacts metallization of the final substrate.
    Type: Application
    Filed: November 28, 2017
    Publication date: March 29, 2018
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • BACKSIDE DEVICE CONTACT
    Publication number: 20180090434
    Abstract: A method for fabricating a backside device contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer, includes forming a trench in the device layer. A trench is formed in the device layer. A sacrificial plug is formed in the trench. The handle wafer is removed to reveal the buried insulator layer. The buried insulator layer is partially removed to expose the sacrificial plug at a bottom of the trench. The sacrificial plug is removed. Backside processing of the buried insulator layer is performed. The trench is filled with a conductor to form a contact plug. A final substrate is connected to the buried insulator layer such that the contact plug contacts metallization of the final substrate.
    Type: Application
    Filed: November 28, 2017
    Publication date: March 29, 2018
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • BACKSIDE DEVICE CONTACT
    Publication number: 20180090433
    Abstract: A method for fabricating a backside device contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer, includes forming a trench in the device layer. The trench is filled with a contact plug. The backside device contact includes the contact plug. After the trench is filled with the contact plug, the handle wafer is removed to reveal the buried insulator layer. The buried insulator layer is partially removed to expose the trench containing the contact plug. A final substrate is connected to the buried insulator layer such that the contact plug contacts metallization of the final substrate. A device structure is formed using the device layer.
    Type: Application
    Filed: November 28, 2017
    Publication date: March 29, 2018
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT
    Publication number: 20180082968
    Abstract: A method of fabricating a pillar-type connection includes forming a first conductive layer. A second conductive layer is formed on the first conductive layer to define a conductive pillar that includes a top surface defining a recess aligned with a hollow core of the first conductive layer. A conductive via that terminates at a top surface of the first conductive layer is formed.
    Type: Application
    Filed: December 1, 2017
    Publication date: March 22, 2018
    Inventors: Charles L. Arvin, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
  • PHOTODIODE STRUCTURES
    Publication number: 20180076351
    Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.
    Type: Application
    Filed: November 8, 2017
    Publication date: March 15, 2018
    Inventors: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON
  • BACKSIDE CONTACT TO A FINAL SUBSTRATE
    Publication number: 20180068892
    Abstract: A device structure with a backside contact includes a silicon-on-insulator substrate including a device layer, a buried insulator layer, and an electrically-conducting connection in a trench. A final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.
    Type: Application
    Filed: November 2, 2017
    Publication date: March 8, 2018
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • BACKSIDE CONTACT TO A FINAL SUBSTRATE
    Publication number: 20180068891
    Abstract: A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming a first switch and a second switch in the device layer. An electrically-conducting connection is formed in a trench. The handle wafer is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.
    Type: Application
    Filed: October 31, 2017
    Publication date: March 8, 2018
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • Conductive pillar shaped for solder confinement
    Patent number: 9911708
    Abstract: A method of fabricating a pillar-type connection includes forming, on a bond pad, a first conductive layer including a hollow core. A second conductive layer is formed on a first conductive layer to define a conductive pillar that includes a non-planar top surface defining a recess aligned with the hollow core.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter
  • Glass interposer with embedded thermoelectric devices
    Patent number: 9913405
    Abstract: The present invention relates generally to integrated circuit (IC) chip packaging, and more particularly, to a structure and method of forming a glass interposer having one or more embedded peltier devices, alongside electrically conductive vias, to help dissipate heat from one or more IC chips in a multi-dimensional chip package through the glass interposer and into an organic carrier, where it can be dissipated into an underlying substrate.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: March 6, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jeffrey P. Gambino, Richard S. Graf, Sudeep Mandal, David J. Russell
  • BACKSIDE CONTACT TO A FINAL SUBSTRATE
    Publication number: 20180040509
    Abstract: A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming an electrically-conducting connection in a trench. The handle wafer is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.
    Type: Application
    Filed: October 19, 2017
    Publication date: February 8, 2018
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • INTEGRATED CIRCUIT INCLUDING WIRE STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE
    Publication number: 20180040556
    Abstract: Various aspects include an integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.
    Type: Application
    Filed: October 18, 2017
    Publication date: February 8, 2018
    Inventors: Edward C. Cooney, III, Jeffrey P. Gambino, Zhong-Xiang He, Robert K. Leidy
  • Backside device contact
    Patent number: 9887156
    Abstract: A back-side device structure with a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, a trench that extends through the device layer and that partially extends through the buried insulator layer, at least one dielectric layer that is formed on the device layer and includes a first opening that communicates with the trench and a contact plug that fills the trench. A final substrate is connected to the buried insulator layer such that the contact plug contacts metallization of the final substrate. The contact plug is externally connected with a source to provide signals to the back-side device structure through a wire formed in the at least one dielectric layer.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • Integrated waveguide structure with perforated chip edge seal
    Patent number: 9874690
    Abstract: An integrated waveguide structure with perforated chip edge seal and methods of manufacture are disclosed herein. The structure includes a guard ring structure surrounding an active region of an integrated circuit chip. The structure further includes a gap in the guard ring structure which is located at a predetermined level of the integrated circuit chip. The structure further includes a waveguide structure formed on a substrate of the integrated circuit chip. The structure further includes a fiber optic optically coupled to the waveguide structure through the gap formed in the guard ring structure.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 23, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jeffrey P. Gambino, Robert K. Leidy, Steven M. Shank
  • Low temperature fabrication of lateral thin film varistor
    Patent number: 9870851
    Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Richard S. Graf, Sudeep Mandal
  • Low temperature fabrication of lateral thin film varistor
    Patent number: 9865674
    Abstract: A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Richard S. Graf, Sudeep Mandal
  • Backside contact to a final substrate
    Patent number: 9852944
    Abstract: Device structures and fabrication methods for a backside contact to a final substrate. An electrically-conducting connection is formed that extends through a device layer of a silicon-on-insulator substrate and partially through a buried insulator layer of the silicon-on-insulator substrate. After the electrically-conducting connection is formed, a handle wafer of the silicon-on-insulator substrate is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is coupled to the buried insulator layer such that the electrically-conducting connection is coupled with the final substrate.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Mark D. Jaffe, Steven M. Shank, Anthony K. Stamper
  • BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE
    Publication number: 20170365775
    Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.
    Type: Application
    Filed: August 30, 2017
    Publication date: December 21, 2017
    Inventors: James W. Adkisson, Panglijen Candra, Thomas J. Dunbar, Jeffrey P. Gambino, Mark D. Jaffe, Anthony K. Stamper, Randy L. Wolf
  • Switchable filters and design structures
    Patent number: 9843303
    Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a fixed electrode with a plurality of fingers on the piezoelectric substrate. The method further includes forming a moveable electrode with a plurality of fingers over the piezoelectric substrate. The method further includes forming actuators aligned with one or more of the plurality of fingers of the moveable electrode.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: December 12, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: James W. Adkisson, Panglijen Candra, Thomas J. Dunbar, Jeffrey P. Gambino, Mark D. Jaffe, Anthony K. Stamper, Randy L. Wolf
  • Integrated circuit including wire structure, related method and design structure
    Patent number: 9831122
    Abstract: An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: November 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Edward C. Cooney, III, Jeffrey P. Gambino, Zhong-Xiang He, Robert K. Leidy
  • Barrier structures for underfill blockout regions
    Patent number: 9798088
    Abstract: The disclosure relates to semiconductor structures and, more particularly, to barrier structures for underfill blockout regions uses in phonotics chip packaging and methods of manufacture. The structure includes a substrate with a plurality of solder connections and at least one optical fiber interface disposed within at least one cavity of the substrate. The structure further includes a barrier structure formed about the cavity which is structured to prevent underfill material from degrading an optical coupling of the optical fiber.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: October 24, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jeffrey P. Gambino, Robert K. Leidy, Wolfgang Sauter, Christopher D. Muzzy, Eric Turcotte, Thomas E. Lombardi