Patents by Inventor Jeffrey P. Kubala

Jeffrey P. Kubala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150277918
    Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Applicant: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa Cranton Heller, Christian Jacobi, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
  • Publication number: 20150277919
    Abstract: According to one aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads. The computer system also includes a multithreading facility configured to control utilization of the configuration to perform a method. Based on determining, by the core in the MT mode, that MT is to be disabled, the MT mode switches to the ST mode, where the primary thread of the MT mode is maintained as the primary thread of the ST mode. A thread context of the one or more secondary threads is made inaccessible to programs. Based on the switching, any one of clearing the program accessible register values or retaining the program accessible register values is performed.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Applicant: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, JR., Dan F. Greiner, Lisa Cranton Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
  • Publication number: 20150277923
    Abstract: Embodiments relate to idle time accumulation in a multithreading computer system. According to one aspect, a computer system includes a configuration having a plurality of cores and an operating system (OS)-image configurable between a single thread (ST) mode and a multithreading (MT) mode in a logical partition. The MT mode supports multiple threads on shared resources per core simultaneously. The computer system also includes a multithreading facility configured to perform a method that includes executing a query instruction on an initiating core of the plurality of cores. The executing includes obtaining, by the OS-image, a maximum thread identification value indicating a current maximum thread identifier of the cores within the logical partition. The initiating core also obtains a multithreading idle time value for each of the cores indicating an aggregate amount of idle time of all threads enabled on each of the cores in the MT mode.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Applicant: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, JR., Dan F. Greiner, Lisa Cranton Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
  • Patent number: 9137120
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: September 15, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, Donald W. Schmidt
  • Patent number: 9110741
    Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 18, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, James H. Mulder, Bernard Pierce, Robert R. Rogers, Donald W. Schmidt
  • Patent number: 9110878
    Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 18, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, James H. Mulder, Bernard Pierce, Robert R. Rogers, Donald W. Schmidt
  • Patent number: 9104509
    Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: August 11, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, James H. Mulder, Bernard Pierce, Robert R. Rogers, Donald W. Schmidt
  • Patent number: 9104508
    Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 11, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, James H. Mulder, Bernard Pierce, Robert R. Rogers, Donald W. Schmidt
  • Patent number: 9098358
    Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: August 4, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, James H. Mulder, Bernard Pierce, Robert R. Rogers, Donald W. Schmidt
  • Patent number: 9098478
    Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: August 4, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, James H. Mulder, Bernard Pierce, Robert R. Rogers, Donald W. Schmidt
  • Publication number: 20150026680
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory.
    Type: Application
    Filed: September 5, 2014
    Publication date: January 22, 2015
    Inventors: Mark S. Farrell, Charles W. Gainey, JR., Jeffrey P. Kubala, Donald W. Schmidt
  • Publication number: 20140337602
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.
    Type: Application
    Filed: July 17, 2014
    Publication date: November 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, Jeffrey P. Kubala, Donald W. Schmidt
  • Publication number: 20140317325
    Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
    Type: Application
    Filed: July 2, 2014
    Publication date: October 23, 2014
    Inventors: Mark S. Farrell, Charles W. Gainey, JR., Jeffrey P. Kubala, James H. Mulder, Bernard Pierce, Robert R. Rogers, Donald W. Schmidt
  • Patent number: 8850450
    Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, James H. Mulder, Bernard Pierce, Robert R. Rogers, Donald W. Schmidt
  • Patent number: 8832689
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mark S Farrell, Charles W Gainey, Jeffrey P Kubala, Donald W Schmidt
  • Patent number: 8819320
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, Donald W. Schmidt
  • Patent number: 8689230
    Abstract: An embodiment provides for operating an information processing system. An aspect of the invention includes allocating an execution interval to a first logical processor of a plurality of logical processors of the information processing system. The execution interval is allocated for use by the first logical processor in executing instructions on a physical processor of the information processing system. The first logical processor determines that a resource required for execution by the first logical processor is locked by another one of the other logical processors. An instruction is issued by the first logical processor to determine whether a lock-holding logical processor is currently running. The lock-holding logical processor waits to release the lock if it is currently running. A command is issued by the first logical processor to a super-privileged process for relinquishing the allocated execution interval by the first logical processor if the locking holding processor is not running.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Greg A. Dyck, Mark S. Farrell, Charles W. Gainey, Jeffrey P. Kubala, Robert R. Rogers, Mark A. Wisniewski
  • Publication number: 20130185736
    Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, JR., Jeffrey P. Kubala, Donald W. Schmidt
  • Publication number: 20130185735
    Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, JR., Jeffrey P. Kubala, James H. Mulder, Bernard Pierce, Robert R. Rogers, Donald W. Schmidt
  • Publication number: 20130185737
    Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, JR., Jeffrey P. Kubala, Donald W. Schmidt