Abstract: A computer readable media, a method, and a system registering a third party application providing an available communication system between a local user and a remote user identity, storing information related to the available communication system in a first database, obtaining contact information for the remote user identity from the third party application, determining a communication type for the third party application, pairing the remote user identity with a contact, and updating a graphical representation of contact information.

Abstract: An exemplary compounding method of controlling a compounding device to prepare an admixture of at least two distinct material sources can include examining material source solutions for incompatibility of the ingredients and operating a first and a second pump to prevent one of the incompatible source solutions from entering a common flow path. The processing method can detect degradation of a fluid line by evaluating one or more of calibration error rate data, cumulative volumetric flow data, or cumulative pump operation data. The processing method can also selectively transfer a first group of source solutions using the first pump, receiving pump data from one or more sensors that sense actions of the pumps, applying fluid correction factors and calculating discrete pump movements, the pump movements being indicative of an amount of source solution displacement by a pump, and operating the pumps to selectively dispense the source solution amounts according to a preparation order.

Abstract: A method for enhancing signal integrity in an interface between a source device and at least one destination device includes: analyzing two or more consecutive data patterns intended to be conveyed by the interface to determine whether data transitions corresponding to the data patterns are likely to introduce coupling noise and/or simultaneous switching output (SSO) effects on the interface; generating a modified data pattern for transmission by the interface, the modified data pattern reducing coupling noise and/or SSO effects on the interface compared to an original data pattern intended to be conveyed by the interface; and transmitting the modified data pattern and information regarding a manner in which the original data pattern was modified to the destination device to thereby reduce coupling noise and/or SSO effects on the interface.

Abstract: Disclosed are embodiments for modeling semiconductor device performance using a single compact model despite changes in performance attribute to model parameter dependency of a single semiconductor device that occur during fitting and/or re-centering due to local layout effects (LLEs) and despite variations in this dependency across multiple related semiconductor devices due to LLEs. In one embodiment, the actual performance attribute to model parameter dependence of a single semiconductor device is fit to a reference dependence so that changes to the compact model are not required even when changes occur in the performance attribute to model parameter dependency during fitting and/or re-centering. In another embodiment, the actual performance attribute to model parameter dependence of each of multiple related semiconductor devices are fit to a reference dependence so that changes to the compact model are not required even when the performance attribute to model parameter dependency varies across the devices.

Abstract: Disclosed are embodiments for modeling semiconductor device performance using a single compact model despite changes in performance attribute to model parameter dependency of a single semiconductor device that occur during fitting and/or re-centering due to local layout effects (LLEs) and despite variations in this dependency across multiple related semiconductor devices due to LLEs. In one embodiment, the actual performance attribute to model parameter dependence of a single semiconductor device is fit to a reference dependence so that changes to the compact model are not required even when changes occur in the performance attribute to model parameter dependency during fitting and/or re-centering. In another embodiment, the actual performance attribute to model parameter dependence of each of multiple related semiconductor devices are fit to a reference dependence so that changes to the compact model are not required even when the performance attribute to model parameter dependency varies across the devices.

Abstract: An apparatus for monitoring at least supply voltage in an IC includes a plurality of monitor circuits distributed throughout the integrated circuit. Each of the monitor circuits is operative to receive the supply voltage, or a signal representative thereof, and to generate an output signal indicative of a comparison between the supply voltage and a reference voltage. The apparatus further includes a control circuit coupled to the plurality of monitor circuits. The control circuit is operative to receive the respective output signals from the plurality of monitor circuits and to generate an output of the apparatus which is a function of information conveyed in the respective output signals from the plurality of monitor circuits.

Abstract: An apparatus for controlling clock skew in an integrated circuit (IC) includes timing circuitry operative to generate a clock signal for distribution in the IC and at least one buffer circuit operative to receive the clock signal, or a signal indicative of the clock signal, and to generate a delayed version of the clock signal as an output thereof. The buffer circuit includes at least first and second inverter stages and a resistive-capacitive (RC) loading structure. An output of the first inverter stage is connected to an input of the second inverter stage via the RC loading structure. The buffer circuit has a delay associated therewith that is selectively varied as a function of one or more adjustable characteristics of the RC loading structure. Clock skew in the IC is controlled as a function of the delay of the buffer circuit.

Abstract: A global power distribution network in an integrated circuit comprising a first layer of conductive material and a second layer of conductive material. The first layer of conductive material may be (i) coupled to one or more power supplies and (ii) configured to form a plurality of first rails of a mesh. The first rails may (a) supply power to one or more components of a core logic of the integrated circuit, (b) be aligned with a first axis of the integrated circuit, and (c) have one or more parameters configured such that the mesh has a uniform voltage gradient from a perimeter of the integrated circuit to a center of the integrated circuit along the first axis. The second layer of conductive material may be (i) coupled to the one or more power supplies and (ii) configured to form a plurality of second rails of the mesh.

Abstract: Disclosed is a closed-loop feedback system for controlling the soft error rate (SER) due to radiation strikes on electronic circuitry. A variable sensitivity soft error rate detector provides and output corresponding to the soft error rate. This output is supplied to a voltage control. The output of the voltage control is fed back to the sensitivity control of the sensor—thus forming a feedback loop. The output of the voltage control may be the power supply of the soft error rate sensor. The output of the soft error rate sensor may also be used to enable and disable fault tolerant schemes or alert a user.

Abstract: A storage medium recording a cell library having one or more cells that may be readable by a computer and may be used by the computer to design an integrated circuit. The one or more cells may have a physical dimension parameter and a channel width parameter. The physical dimension parameter may be a footprint of the one or more cells. The channel width parameter may have a minimum driver size and a maximum driver size. The channel width parameter may define a range within which a tool varies the channel width between the maximum driver size and the minimum driver size during a design flow of the integrated circuit based upon one or more power criteria without changing the footprint.

Abstract: An apparatus for monitoring at least supply voltage in an IC includes a plurality of monitor circuits distributed throughout the integrated circuit. Each of the monitor circuits is operative to receive the supply voltage, or a signal representative thereof, and to generate an output signal indicative of a comparison between the supply voltage and a reference voltage. The apparatus further includes a control circuit coupled to the plurality of monitor circuits. The control circuit is operative to receive the respective output signals from the plurality of monitor circuits and to generate an output of the apparatus which is a function of information conveyed in the respective output signals from the plurality of monitor circuits.

Abstract: An apparatus for controlling clock skew in an integrated circuit (IC) includes timing circuitry operative to generate a clock signal for distribution in the IC and at least one buffer circuit operative to receive the clock signal, or a signal indicative of the clock signal, and to generate a delayed version of the clock signal as an output thereof. The buffer circuit includes at least first and second inverter stages and a resistive-capacitive (RC) loading structure. An output of the first inverter stage is connected to an input of the second inverter stage via the RC loading structure. The buffer circuit has a delay associated therewith that is selectively varied as a function of one or more adjustable characteristics of the RC loading structure. Clock skew in the IC is controlled as a function of the delay of the buffer circuit.

Abstract: An apparatus and method for providing a read-only memory (ROM) bit cell having one each of a PMOS transistor and an NMOS transistor, which has reduced static and dynamic electric power losses, are described. In particular, the bit cell does not require a pre-charge transistor. The sense amplifier for determining the voltages on ROM bit lines may be a digital inverter, address decoding may be simplified since there are no timing requirements with respect to transistor pre-charge, and chips containing a plurality of ROM bit cell may be readily programmed. In one embodiment of the invention, each bit cell includes one PMOS transistor having its source in electrical connection with a voltage source, its drain connected or unconnected to a bit line, and its gate connected to an inverted version of the word line signal; and one NMOS transistor having its source connected to a lower voltage source, its drain connected or disconnected to the bit line, and its gate connected to the word line.

Abstract: A storage medium recording a cell library having one or more cells that may be readable by a computer and may be used by the computer to design an integrated circuit. The one or more cells may have a physical dimension parameter and a channel width parameter. The physical dimension parameter may be a footprint of the one or more cells. The channel width parameter may have a minimum driver size and a maximum driver size. The channel width parameter may define a range within which a tool varies the channel width between the maximum driver size and the minimum driver size during a design flow of the integrated circuit based upon one or more power criteria without changing the footprint.

Abstract: A memory for an integrated circuit, a method of designing a memory and an integrated circuit manufactured by the method. In one embodiment, the memory includes: (1) one of: (1a) at least one data input register block and at least one bit enable input register block and (1b) at least one data and bit enable merging block and at least one merged data register block, (2) one of: (2a) at least one address input register block and at least one binary to one-hot address decode block and (2b) at least one binary to one-hot address decode block and at least one one-hot address register block and (3) a memory array, at least one of the blocks having a timing selected to match at least some timing margins outside of the memory.

Abstract: A global power distribution network in an integrated circuit comprising a first layer of conductive material and a second layer of conductive material. The first layer of conductive material may be (i) coupled to one or more power supplies and (ii) configured to form a plurality of first rails of a mesh. The first rails may (a) supply power to one or more components of a core logic of the integrated circuit, (b) be aligned with a first axis of the integrated circuit, and (c) have one or more parameters configured such that the mesh has a uniform voltage gradient from a perimeter of the integrated circuit to a center of the integrated circuit along the first axis. The second layer of conductive material may be (i) coupled to the one or more power supplies and (ii) configured to form a plurality of second rails of the mesh.

Abstract: A method for conserving power in a device. The method generally includes the steps of (A) generating a polarity signal by analyzing a current one of a plurality of data items having a plurality of data bits, the polarity signal having an inversion bit indicating that the current data item is to be stored in one of (i) an inverted condition and (ii) a non-inverted condition relative to a normal condition such that a majority of the data bits have a first logic state, wherein reading one of the data bits having the first logic state consumes less power than reading one of the data bits having a second logic state, (B) selectively either (i) inverting the current data item or (ii) not inverting current the data item based on the inversion bit and (C) storing the current data item in a plurality of single-ended bit cells in the device.

Abstract: A method to analyze timing in a circuit, generally including (A) simulating reception of an input signal and a clock signal at a first flip-flop, wherein (i) the input signal has a latest transition, (ii) the input signal arrives through a first path and (iii) the clock signal has an active edge, (B) calculating a value of a time difference between the latest transition and the active edge, (C) calculating a delay between the active edge and the latest transition appearing in an output signal, wherein (i) the delay is based on a model responding to the value, (ii) the model characterizes a clock-to-output delay as a function of the time difference and (iii) the characterization covering a range of values, (D) calculating an arrival time of the latest transition at a second flip-flop through a second signal path and (E) storing the arrival time in a recording medium.

Abstract: Disclosed is a closed-loop feedback system for controlling the soft error rate (SER) due to radiation strikes on electronic circuitry. A variable sensitivity soft error rate detector provides and output corresponding to the soft error rate. This output is supplied to a voltage control. The output of the voltage control is fed back to the sensitivity control of the sensor—thus forming a feedback loop. The output of the voltage control may be the power supply of the soft error rate sensor. The output of the soft error rate sensor may also be used to enable and disable fault tolerant schemes or alert a user.

Abstract: Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad one the packaged chip is placed in system. No additional pins on the package are necessary.