Patents by Inventor Jeffrey S. Cope

Jeffrey S. Cope has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
    Patent number: 5960270
    Abstract: A method for forming a metal gate MOS transistor begins by forming source and drain electrodes (26, 28, and/or 118) within a substrate (12 or 102). These source and drain regions (26, 28, and 118) are self-aligned to a lithographically-patterned feature (24 or 108). After formation of the source and drain regions, the features (24 and 108 are processed to fill these features with a metallic gate layer (28a or 128a). This metal layer (28a or 128a) is then chemically mechanically polished (CMPed) to form a metallic plug region (28b or 128b) within the features (24 or 108). The plug region (28b or 128b) is formed in either an inlaid or dual inlaid manner wherein this metallic plug region (28b or 128b) is self-aligned to the previously formed source and drain regions and preferably functions as a metal MOS gate region.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: September 28, 1999
    Assignee: Motorola, Inc.
    Inventors: Veena Misra, Suresh Venkatesan, Christopher C. Hobbs, Brad Smith, Jeffrey S. Cope, Earnest B. Wilson