Abstract: A method and system for providing direct execution of a serializing instruction in a processor is disclosed. The processor has the serializing instruction and a nonserializing instruction. The processor includes execution logic having a pipeline for executing the nonserializing instruction. The processor also includes logic separate from the execution logic for executing the serializing instruction. The method and system include recognizing the serializing instruction, recognizing the nonserializing instruction, providing the nonserializing instruction to the execution logic, and providing the serializing instruction to the separate logic. The serializing instruction is executed without providing the serializing instruction to the pipeline.

Abstract: In a data processing system having a processor, which dispatches floating point instructions to a floating point unit, a checkpoint table is associated with a floating point register rename table for restoring the state of the floating point register rename table upon the occurrence of a mispredicted branch or an interrupt. This is accomplished (1) using a program order tag associated with each one of the instructions, (2) by replacing the valid bit vector of the floating point register rename table with the valid bit vector of a checkpoint entry whose program order tag is the oldest among all checkpoint entries that have a program order tag younger or as old as the program order tag of the mispredicted branch or the interrupted instruction, and (3) by using the location portion of the checkpoint entry to replace the NEXT pointer of the register renaming table.

Abstract: A system and method for forwarding a first instruction into a second instruction in a processor is disclosed. The processor comprises an execution unit and providing a plurality of instructions. The first instruction depends upon execution of the second instruction but does not otherwise require execution by the execution unit. The method first searches for the second instruction. The method then forwards the first instruction via the second instruction by appending a tag to the second instruction, the tag identifying the first instruction.One aspect of the method and system forwards a store instruction into a floating point instruction in a processor. The store instruction has a source address and the floating point instruction has a target address. The processor provides a plurality of instructions. The method searches for the floating point instruction that is provided before the store instruction. The method then determines if the source address is equal to the target address.

Abstract: An apparatus and method reduces the number of rename registers for a floating point status and control register (FPSCR) in a superscalar microprocessor executing out of order/speculative instructions. A floating point queue (FPQ) receives speculative instructions and issues out-of-order instructions to FPQ execution units, each instruction containing a group identifier tag (GID) and a target identifier tag (TID). The GID tag indicates a set of instructions bounded by interruptible or branch instructions. The TID indicates a targeted architected facility and the program order of the instruction. The FPSCR contains status and control bits for each instruction and is updated when an instruction is executed and committed.