Patents by Inventor Jeffrey Venuti
Jeffrey Venuti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9698759Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.Type: GrantFiled: May 5, 2014Date of Patent: July 4, 2017Assignee: ANALOG DEVICES, INC.Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
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Patent number: 9312831Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.Type: GrantFiled: October 1, 2013Date of Patent: April 12, 2016Assignee: ANALOG DEVICES, INC.Inventors: Eric Nestler, Vladimir Zlatkovic, Jeffrey Venuti
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Publication number: 20150381146Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.Type: ApplicationFiled: May 5, 2014Publication date: December 31, 2015Applicant: Analog Devices, Inc.Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
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Patent number: 9036420Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: GrantFiled: May 15, 2012Date of Patent: May 19, 2015Assignee: ANALOG DEVICES, INC.Inventors: Benjamin Vigoda, Jeffrey Bernstein, Jeffrey Venuti, Alexander Alexeyev, Eric Nestler, David Reynolds, William Bradley, Vladimir Zlatkovic
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Publication number: 20140233773Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.Type: ApplicationFiled: October 1, 2013Publication date: August 21, 2014Applicant: Analog Devices, Inc.Inventors: Eric Nestler, Vladimir Zlatkovic, Jeffrey Venuti
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Patent number: 8717094Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.Type: GrantFiled: June 6, 2012Date of Patent: May 6, 2014Assignee: Analog Devices, Inc.Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
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Patent number: 8547272Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.Type: GrantFiled: August 18, 2011Date of Patent: October 1, 2013Assignee: Analog Devices, Inc.Inventors: Eric Nestler, Vladimir Zlatkovic, Jeffrey Venuti
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Publication number: 20130207827Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.Type: ApplicationFiled: August 18, 2011Publication date: August 15, 2013Applicant: Analog Devices, Inc.Inventors: Eric Nestler, Vladimir Zlatkovic, Jeffrey Venuti
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Publication number: 20130094298Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: ApplicationFiled: May 15, 2012Publication date: April 18, 2013Applicant: Analog Devices, Inc.Inventors: Benjamin Vigoda, Eric Nestler, Jeffrey Bernstein, David Reynolds, Alexander Alexeyev, Jeffrey Venuti, William Bradley, Vladimir Ziatkovic
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Publication number: 20120306569Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.Type: ApplicationFiled: June 6, 2012Publication date: December 6, 2012Applicant: Analog Devices, Inc.Inventors: Eric Nestler, Jeffrey Venuti, Vladimir Zlatkovic, Kartik Nanda
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Patent number: 8179731Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: GrantFiled: August 6, 2009Date of Patent: May 15, 2012Assignee: Analog Devices, Inc.Inventors: Benjamin Vigoda, Eric Nestler, Jeffrey Bernstein, David Reynolds, Alexander Alexeyev, Jeffrey Venuti, William Bradley, Vladimir Zlatkovic
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Patent number: 8107306Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: GrantFiled: August 6, 2009Date of Patent: January 31, 2012Assignee: Analog Devices, Inc.Inventors: Benjamin Vigoda, Eric Nestler, Jeffrey Bernstein, David Reynolds, Alexander Alexeyev, Jeffrey Venuti, William Bradley, Vladimir Zlatkovic
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Publication number: 20100281089Abstract: A circuit includes a signal processing circuit for accepting an input and for generating a set of outputs. The input is provided in an input range that has a set of representative values, and each output represents a measure of an association of the input with one or more of the representative values. The signal processing circuit includes a group of output sections, each output section being responsive to the input of the signal processing circuit. Each output section includes one or more sigmoid generators. Each sigmoid generator is responsive to an input of the output section to generate an output that represents a sigmoid function of the input of the output section. Each output section also includes a circuitry for combining the outputs of the one or more sigmoid generators to form one of the set of outputs of the signal processing circuit. An input transformation circuit is coupled to the plurality of output sections.Type: ApplicationFiled: March 2, 2010Publication date: November 4, 2010Applicant: Lyric Semiconductor, Inc.Inventors: Benjamin Vigoda, Jeffrey Bernstein, Alexander Alexeyev, Jeffrey Venuti
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Publication number: 20100246287Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: ApplicationFiled: August 6, 2009Publication date: September 30, 2010Applicant: Lyric Semiconductor, Inc.Inventors: Benjamin Vigoda, Jeffrey Bernstein, Jeffrey Venuti, David Reynolds, Alexander Alexeyev
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Publication number: 20100246289Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: ApplicationFiled: August 6, 2009Publication date: September 30, 2010Applicant: Lyric Semiconductor, Inc.Inventors: Benjamin Vigoda, Jeffrey Bernstein, Jeffrey Venuti, David Reynolds, Alexander Alexeyev
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Publication number: 20100220514Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.Type: ApplicationFiled: August 6, 2009Publication date: September 2, 2010Applicant: Lyric Semiconductor, Inc.Inventors: Benjamin Vigoda, Jeffrey Bernstein, Jeffrey Venuti, Alexander Alexeyev, Eric Nestler, David Reynolds