Patents by Inventor Jen-Inn Chyi

Jen-Inn Chyi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11515307
    Abstract: A method of making a semiconductor device includes: providing a substrate; forming an insulating layer on the substrate; forming a first trench in the insulating layer; forming a first semiconductor layer in the first trench; and removing a portion of the insulating layer to expose the first semiconductor layer.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: November 29, 2022
    Assignees: National Applied Research Laboratories, EPISTAR Corporation
    Inventors: Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Wen-Kuan Yeh, Jen-Inn Chyi, Meng-Yang Chen, Rong-Ren Lee, Shih-Chang Lee, Ta-Cheng Hsu
  • Patent number: 11049961
    Abstract: A high electron mobility transistor, includes a substrate; a channel layer formed on the substrate; a barrier layer formed on the channel layer; a source electrode and a drain electrode formed on the barrier layer; a depletion layer formed on the barrier layer and between the source electrode and the drain electrode, wherein a material of the depletion layer comprises boron nitride or zinc oxide; and a gate electrode formed on the depletion layer.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 29, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Shang-Ju Tu, Chia-Cheng Liu, Tsung-Cheng Chang, Ya-Yu Yang, Yu-Jiun Shen, Jen-Inn Chyi
  • Patent number: 10868128
    Abstract: Semiconductor contact structures, a semiconductor device including the semiconductor contact structures, and a method for forming the same are disclosed. In an embodiment, a semiconductor device includes a channel layer on a substrate; an interface layer on the channel layer, the interface layer including titanium (Ti), the interface layer contacting the channel layer; and a contact metal layer over the interface layer, the contact metal layer including aluminum silicon copper alloy (AlSiCu).
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: December 15, 2020
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Jen-Inn Chyi, Cheng-Han Tsou, Szu-Hung Chen
  • Publication number: 20200303377
    Abstract: A method of making a semiconductor device includes: providing a substrate; forming an insulating layer on the substrate; forming a first trench in the insulating layer; forming a first semiconductor layer in the first trench; and removing a portion of the insulating layer to expose the first semiconductor layer.
    Type: Application
    Filed: June 4, 2020
    Publication date: September 24, 2020
    Inventors: Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Wen-Kuan Yeh, Jen-Inn Chyi, Meng-Yang Chen, Rong-Ren Lee, Shih-Chang Lee, Ta-Cheng Hsu
  • Patent number: 10727231
    Abstract: A heterogeneously integrated semiconductor device includes a substrate comprising a first material; a recess formed within the substrate and having a bottom portion with a first width, a top portion with a second width and a middle portion with a third width larger than the first width and the second width; and a first semiconductor layer filled in the bottom portion and including a second material different from the first material.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: July 28, 2020
    Assignees: National Applied Research Laboratories, EPISTAR Corporation
    Inventors: Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Wen-Kuan Yeh, Jen-Inn Chyi, Meng-Yang Chen, Rong-Ren Lee, Shih-Chang Lee, Ta-Cheng Hsu
  • Publication number: 20200006543
    Abstract: A high electron mobility transistor, includes a substrate; a channel layer formed on the substrate; a barrier layer formed on the channel layer; a source electrode and a drain electrode formed on the barrier layer; a depletion layer formed on the barrier layer and between the source electrode and the drain electrode, wherein a material of the depletion layer comprises boron nitride or zinc oxide; and a gate electrode formed on the depletion layer.
    Type: Application
    Filed: June 26, 2019
    Publication date: January 2, 2020
    Inventors: Shang-Ju TU, Chia-Cheng LIU, Tsung-Cheng CHANG, Ya-Yu YANG, Yu-Jiun SHEN, Jen-Inn CHYI
  • Publication number: 20200006511
    Abstract: Semiconductor contact structures, a semiconductor device including the semiconductor contact structures, and a method for forming the same are disclosed. In an embodiment, a semiconductor device includes a channel layer on a substrate; an interface layer on the channel layer, the interface layer including titanium (Ti), the interface layer contacting the channel layer; and a contact metal layer over the interface layer, the contact metal layer including aluminum silicon copper alloy (AlSiCu).
    Type: Application
    Filed: February 1, 2019
    Publication date: January 2, 2020
    Inventors: Jen-Inn Chyi, Cheng-Han Tsou, Szu-Hung Chen
  • Patent number: 10379078
    Abstract: A biosensor includes a transistor and a reactive electrode. The transistor has a source, a drain and a gate surface disposed therebetween. The reactive electrode is spaced apart from the gate surface of the transistor, has a receptor immobilized thereon for specific binding with an analyte in a liquid sample, and is configured to contact the liquid sample together with the gate surface of the transistor.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: August 13, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Yu-Lin Wang, Jen-Inn Chyi, Chia-Ho Chu, Indu Sarangadharan
  • Patent number: 10283631
    Abstract: In one aspect of the present disclosure, a semiconductor device includes a channel layer, an AlxIn1-xN layer on the channel layer with a thickness of t1, and a reverse polarization layer on the AlxIn1-xN layer with a thickness of t2. The thickness is 0.5×t1?t2?3×t1. In another aspect of the present disclosure, a method of manufacturing a semiconductor device is provided. The method including: forming a channel layer on a substrate; forming an AlxIn1-xN layer on the channel layer with a thickness of t1; and forming a reverse polarization layer on the AlxIn1-xN layer with a thickness of t2. The thickness is 0.5×t1?t2?3×t1.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: May 7, 2019
    Assignees: DELTA ELECTRONICS, INC., NATIONAL CENTRAL UNIVERSITY
    Inventors: Chun-Chieh Yang, Jen-Inn Chyi, Geng-Yen Lee
  • Publication number: 20190043862
    Abstract: A heterogeneously integrated semiconductor device includes a substrate comprising a first material; a recess formed within the substrate and having a bottom portion with a first width, a top portion with a second width and a middle portion with a third width larger than the first width and the second width; and a first semiconductor layer filled in the bottom portion and including a second material different from the first material.
    Type: Application
    Filed: October 12, 2018
    Publication date: February 7, 2019
    Inventors: Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Wen-Kuan Yeh, Jen-Inn Chyi, Meng-Yang Chen, Rong-Ren Lee, Shih-Chang Lee, Ta-Cheng Hsu
  • Patent number: 10134735
    Abstract: A heterogeneously integrated semiconductor devices includes a base substrate; a Ge-containing film formed on the base substrate; a PMOSFET transistor having a first fin formed on the Ge-containing film; and a NMOSFET transistor having a second fin formed on the Ge-containing film; wherein the PMOSFET transistor and the NMOSFET transistor compose a CMOS transistor, and the first fin comprises Ge-containing material and the second fin comprises a Group III-V compound.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: November 20, 2018
    Assignees: National Applied Research Laboratories, EPISTAR Corporation
    Inventors: Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Wen-Kuan Yeh, Jen-Inn Chyi, Meng-Yang Chen, Rong-Ren Lee, Shih-Chang Lee, Ta-Cheng Hsu
  • Patent number: 10107824
    Abstract: A method for analyzing concentration of a cardiovascular disease (CVD) biomarker in a liquid sample includes: applying the liquid sample to a biosensor, the biosensor including a transistor having a drain, a source, and a gate terminal disposed between the gate and the source, and a reactive electrode spaced apart from the gate terminal of the transistor and having a receptor immobilized thereon for specific binding with the CVD biomarker, the liquid sample being in contact with the gate terminal and the reactive electrode; applying a voltage pulse between the reactive electrode and the source, the voltage pulse having a pulse width; monitoring a response current in response to the voltage pulse; and analyzing the response current.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: October 23, 2018
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Yu-Lin Wang, Gwo-Bin Lee, Shu-Chu Shiesh, Jen-Inn Chyi, Abiral Regmi, Indu Sarangadharan, Chen-Pin Hsu
  • Publication number: 20170373064
    Abstract: A heterogeneously integrated semiconductor devices includes a base substrate; a Ge-containing film formed on the base substrate; a PMOSFET transistor having a first fin formed on the Ge-containing film; and a NMOSFET transistor having a second fin formed on the Ge-containing film; wherein the PMOSFET transistor and the NMOSFET transistor compose a CMOS transistor, and the first fin comprises Ge-containing material and the second fin comprises a Group III-V compound.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 28, 2017
    Inventors: Shih-Pang Chang, Guang-Li Luo, Szu-Hung Chen, Wen-Kuan Yeh, Jen-Inn Chyi, Meng-Yang Chen, Rong-Ren Lee, Shih-Chang Lee, Ta-Cheng Hsu
  • Patent number: 9752972
    Abstract: A viscosity measurement system, which is for measuring the viscosity of a fluid, comprises a transistor-type viscosity sensor, an electrical measurement unit, and a processing unit. The transistor-type viscosity sensor includes a semiconductor structure, a source terminal, and a drain terminal. The semiconductor structure includes a GaN layer and an AlGaN layer disposed on the GaN layer. The portion of the semiconductor structure that is between the source terminal and the drain terminal has a gate region, which has an exposed surface for being in contact with the fluid. The electrical measurement unit is in electrical connection with the source terminal and the drain terminal and for measuring an electronic signal of the semiconductor structure. The processing unit is coupled to the electrical measurement unit and for determining the viscosity of the fluid according to the electronic signal measured.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: September 5, 2017
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Yu-Lin Wang, Jen-Inn Chyi, Jung-Ying Fang
  • Patent number: 9640672
    Abstract: A diode device including a III-N compound layer is provided. The III-N compound layer has a channel region therein. A cathode region is located on the III-N compound layer. A first anode region is located on the III-N compound layer and extends into the III-N compound layer. The bottom of the first anode region is under the channel region. A second anode region is located on the III-N compound layer between the cathode region and the first anode region, and extends into the III-N compound material layer. The second anode region includes a high-energy barrier region. The high-energy barrier region adjoins a sidewall of the first anode region. A method for manufacturing a diode device is also provided.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: May 2, 2017
    Assignees: National Central University, Delta Electronics, Inc.
    Inventors: Jen-Inn Chyi, Bo-Shiang Wang, Chun-Chieh Yang, Geng-Yen Lee
  • Publication number: 20170016916
    Abstract: A method for analyzing concentration of a cardiovascular disease (CVD) biomarker in a liquid sample includes: applying the liquid sample to a biosensor, the biosensor including a transistor having a drain, a source, and a gate terminal disposed between the gate and the source, and a reactive electrode spaced apart from the gate terminal of the transistor and having a receptor immobilized thereon for specific binding with the CVD biomarker, the liquid sample being in contact with the gate terminal and the reactive electrode; applying a voltage pulse between the reactive electrode and the source, the voltage pulse having a pulse width; monitoring a response current in response to the voltage pulse; and analyzing the response current.
    Type: Application
    Filed: September 27, 2016
    Publication date: January 19, 2017
    Applicant: National Tsing Hua University
    Inventors: Yu-Lin WANG, Gwo-Bin LEE, Shu-Chu SHIESH, Jen-Inn CHYI, Abiral REGMI, Indu SARANGADHARAN, Chen-Pin HSU
  • Publication number: 20160336436
    Abstract: In one aspect of the present disclosure, a semiconductor device includes a channel layer, an AlxIn1-xN layer on the channel layer with a thickness of t1, and a reverse polarization layer on the AlxIn1-xN layer with a thickness of t2. The thickness is 0.5×t1?t2?3×t1. In another aspect of the present disclosure, a method of manufacturing a semiconductor device is provided. The method including: forming a channel layer on a substrate; forming an AlxIn1-xN layer on the channel layer with a thickness of t1; and forming a reverse polarization layer on the AlxIn1-xN layer with a thickness of t2. The thickness is 0.5×t1?t2?3×t1.
    Type: Application
    Filed: May 12, 2016
    Publication date: November 17, 2016
    Inventors: Chun-Chieh YANG, Jen-Inn CHYI, Geng-Yen LEE
  • Publication number: 20160315204
    Abstract: A diode device including a III-N compound layer is provided. The III-N compound layer has a channel region therein. A cathode region is located on the III-N compound layer. A first anode region is located on the III-N compound layer and extends into the III-N compound layer. The bottom of the first anode region is under the channel region. A second anode region is located on the III-N compound layer between the cathode region and the first anode region, and extends into the III-N compound material layer. The second anode region includes a high-energy barrier region. The high-energy barrier region adjoins a sidewall of the first anode region. A method for manufacturing a diode device is also provided.
    Type: Application
    Filed: February 10, 2016
    Publication date: October 27, 2016
    Inventors: JEN-INN CHYI, BO-SHIANG WANG, CHUN-CHIEH YANG, GENG-YEN LEE
  • Publication number: 20160305900
    Abstract: A biosensor includes a transistor and a reactive electrode. The transistor has a source, a drain and a gate surface disposed therebetween. The reactive electrode is spaced apart from the gate surface of the transistor, has a receptor immobilized thereon for specific binding with an analyte in a liquid sample, and is configured to contact the liquid sample together with the gate surface of the transistor.
    Type: Application
    Filed: October 2, 2015
    Publication date: October 20, 2016
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Yu-Lin WANG, Jen-Inn CHYI, Chia-Ho CHU, Indu SARANGADHARAN
  • Patent number: 9214518
    Abstract: Disclosed is a wafer comprising a first layer of GaSb grown on a GaSb substrate by molecular beam epitaxy (MBE), an oxide layer deposited on the surface of the first layer, and a cap layer deposited on the surface of the oxide layer. The wafer was capped with an arsenic (As) layer after the growth of the first layer. The As layer was removed from the wafer before the oxide layer was deposited on the surface of the first layer. Also disclosed is a method of forming a wafer. The method comprises growing a first layer of GaSb on a GaSb substrate by MBE, capping the wafer with an As layer after the growth of the first layer, removing the As layer from the wafer, depositing an oxide layer on the surface of the first layer, and depositing a cap layer on the surface of the oxide layer.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: December 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited and National Taiwan University
    Inventors: Jui-Lin Chu, Ming-Hwei Hong, Juei-Nai Kwo, Tun-Wen Pi, Jen-Inn Chyi