Patents by Inventor Jen-Kuang Fang

Jen-Kuang Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190348344
    Abstract: A connection structure is provided. The connection structure includes an intermediate conductive layer, a first conductive layer and a second conductive layer. The intermediate conductive layer includes a first surface and a second surface opposite to the first surface. The intermediate conductive layer has a first coefficient of thermal expansion. The first conductive layer is in contact with the first surface of the intermediate conductive layer. The first conductive layer has a second CTE. The second conductive layer is in contact with the second surface of the intermediate conductive layer. The first conductive layer and the second conductive layer are formed of the same material. One of the first CTE and the second CTE is negative, and the other is positive.
    Type: Application
    Filed: May 8, 2018
    Publication date: November 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen-Long LU, Jen-Kuang FANG
  • Publication number: 20190229054
    Abstract: A package device includes a circuit layer, at least one conductive segment, an encapsulant and a redistribution layer. The conductive segment is disposed on the circuit layer and has a first surface and a second surface. The encapsulant encapsulates at least a portion of the conductive segment and has a first upper surface. A first portion of the first surface and at least a portion of the second surface of the conductive segment are disposed above the first upper surface of the encapsulant. The redistribution layer is disposed on the encapsulant, the first portion of the first surface of the conductive segment, and the second surface of the conductive segment.
    Type: Application
    Filed: January 25, 2018
    Publication date: July 25, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen-Long LU, Jen-Kuang FANG, Min Lung HUANG, Chan Wen LIU, Ching Kuo HSU
  • Publication number: 20190157197
    Abstract: A semiconductor device package includes an electronic component, a first substrate, a first bonding wire and a second substrate. The electronic component has a first surface. The first substrate is disposed on the first surface of the electronic component. The first bonding wire electrically connects the first substrate to the electronic component. The second substrate is disposed on the first surface of the electronic component. The second substrate defines an opening accommodating the first substrate and the first bonding wire.
    Type: Application
    Filed: November 22, 2017
    Publication date: May 23, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jen-Kuang FANG, Wen-Long LU
  • Patent number: 10269672
    Abstract: A semiconductor package device comprises a first dielectric layer, a first conductive pad and a first conductive element. The first dielectric layer has a first surface and a second surface opposite to the first surface. The first dielectric layer defines a first opening tapered from the first surface toward the second surface. The first conductive pad is within the first opening and adjacent to the second surface of the first dielectric layer. At least a portion of the first conductive element is within the first opening. The first conductive element is engaged with (e.g., abuts) a sidewall of the first opening, the first conductive element having a first surface facing toward the first conductive pad, wherein the first surface of the first conductive element is spaced apart from the first conductive pad.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: April 23, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jen-Kuang Fang, Wen-Long Lu
  • Publication number: 20190096823
    Abstract: A semiconductor package device comprises an electronic component, a conductive bump and a first conductive layer. The electronic component has a top surface. The conductive bump is disposed on the top surface of the electronic component. The conductive bump includes a main body and a protruding portion. The first conductive layer covers a portion of the protruding portion. The first conductive layer has a first upper surface and a second upper surface. The first upper surface and the second upper surface are not coplanar.
    Type: Application
    Filed: September 27, 2017
    Publication date: March 28, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jen-Kuang FANG, Wen-Long LU
  • Patent number: 10224301
    Abstract: A semiconductor package device includes a carrier, a first electronic component, and a conductive element on the carrier. The first electronic component is over the carrier. The conductive element is on the carrier and electrically connects the first electronic component to the carrier. The conductive element includes at least one conductive particle and a solder material covering the conductive particle, and the conductive particle includes a metal core, a barrier layer covering the metal core, and a metal layer covering the barrier layer.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: March 5, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jen-Kuang Fang, Wen-Long Lu
  • Publication number: 20190067142
    Abstract: A semiconductor package device comprises a first dielectric layer, a first conductive pad and a first conductive element. The first dielectric layer has a first surface and a second surface opposite to the first surface. The first dielectric layer defines a first opening tapered from the first surface toward the second surface. The first conductive pad is within the first opening and adjacent to the second surface of the first dielectric layer. At least a portion of the first conductive element is within the first opening. The first conductive element is engaged with (e.g., abuts) a sidewall of the first opening, the first conductive element having a first surface facing toward the first conductive pad, wherein the first surface of the first conductive element is spaced apart from the first conductive pad.
    Type: Application
    Filed: August 24, 2017
    Publication date: February 28, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jen-Kuang FANG, Wen-Long LU
  • Publication number: 20190051590
    Abstract: A semiconductor package device includes a circuit layer having a top surface, a first electronic component disposed on the top surface of the circuit layer, and a first conductive element disposed on the top surface of the circuit layer, the first conductive element having a top surface. The first electronic component has an active surface and a back surface facing the top surface of the circuit layer. A distance between the active surface of the first electronic component and the top surface of the circuit layer is greater than a distance between the top surface of the first conductive element and the top surface of the circuit layer.
    Type: Application
    Filed: August 9, 2017
    Publication date: February 14, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jen-Kuang FANG, Wen-Long LU
  • Publication number: 20190013284
    Abstract: A semiconductor package device includes a carrier, a first electronic component, and a conductive element on the carrier. The first electronic component is over the carrier. The conductive element is on the carrier and electrically connects the first electronic component to the carrier. The conductive element includes at least one conductive particle and a solder material covering the conductive particle, and the conductive particle includes a metal core, a barrier layer covering the metal core, and a metal layer covering the barrier layer.
    Type: Application
    Filed: July 5, 2017
    Publication date: January 10, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jen-Kuang FANG, Wen-Long LU
  • Publication number: 20190013289
    Abstract: A semiconductor device package includes an electronic component, a first set of conductive wires electrically connected to the electronic component, and an insulation layer surrounding the first set of conductive wires. The insulation layer exposes a portion of the first set of the conductive wires. The insulation layer is devoid of a filler.
    Type: Application
    Filed: July 10, 2017
    Publication date: January 10, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jen-Kuang FANG, Wen-Long LU
  • Patent number: 9748196
    Abstract: The present disclosure relates to a semiconductor package structure, including a die and a package substrate. The die includes a semiconductor substrate, multiple interconnect metal layers, and at least one inter-level dielectric disposed between ones of the interconnect metal layers. Each inter-level dielectric is formed of a low k material. An outermost interconnect metal layer has multiple first conductive segments exposed from a surface of the inter-level dielectric. The package substrate includes a substrate body and multiple second conductive segments exposed from a surface of the substrate body. The second conductive segments are electrically connected to the first conductive segments.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: August 29, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jen-Kuang Fang, Kuo-Hua Chen
  • Publication number: 20160079157
    Abstract: The present disclosure relates to a semiconductor package structure, including a die and a package substrate. The die includes a semiconductor substrate, multiple interconnect metal layers, and at least one inter-level dielectric disposed between ones of the interconnect metal layers. Each inter-level dielectric is formed of a low k material. An outermost interconnect metal layer has multiple first conductive segments exposed from a surface of the inter-level dielectric. The package substrate includes a substrate body and multiple second conductive segments exposed from a surface of the substrate body. The second conductive segments are electrically connected to the first conductive segments.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 17, 2016
    Inventors: Jen-Kuang FANG, Kuo-Hua CHEN
  • Patent number: 7726544
    Abstract: A method of forming pre-solders on a substrate is provided. Firstly, a substrate is provided. The substrate includes an upper surface and a lower surface. There are several metal circuits and a solder mask both on the upper and the lower surfaces. Each solder mask covers parts of the corresponding metal circuits and parts of the corresponding surface for exposing parts of several pads of the corresponding metal circuits. Then, a patterned photo-resist film is formed on the upper surface. The patterned photo-resist film has several openings for exposing the upper-surface pads. Afterwards, several metal materials are formed in the opening by printing. Thereon, the metal materials are reflown to form several pre-solders on the upper-surface pads. Finally, the patterned photo-resist film is removed.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: June 1, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Jen-Kuang Fang, Chung-Hwa Feng
  • Patent number: 7635610
    Abstract: A multi-chip stack package includes a substrate, a first chip, a second chip, a plurality of bumps, a plurality of junction interface bumps, a plurality of conductive wires, a filler material and an encapsulating material. The substrate has a plurality of first contacts and a plurality of second contacts thereon. The first chip is bonded to the substrate surface by the bumps positioned between the active surface of the first chip and the first contacts. The second chip is bonded to the first chip by the junction interface bumps positioned between the back surface of the first chip and the back surface of the second chip. The conductive wires electrically connect the active surface of the second chip and the second contacts. The filler material encloses the bumps and the junction interface bumps. The encapsulating material encloses the first chip, the second chip and the conductive wires.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: December 22, 2009
    Assignee: Adavnaced Semiconductor Engineering Inc.
    Inventor: Jen-Kuang Fang
  • Patent number: 7384566
    Abstract: A fabrication method for PCBs. The method includes providing a substrate having a layout area and a periphery area around the layout area on a surface, forming a patterned wiring layer, having a bus line in the periphery area, a plurality of pads in the layout area, a plurality of bridge lines providing electrical connection between the pads, and a plating line electrically connecting the bus line and pads, overlying the substrate, forming a patterned solder mask over the substrate and wiring layer, the patterned solder mask having a plurality of first openings respectively exposing the pads and plating a metal layer respectively overlying the pads, forming a plurality of second openings respectively exposing the bridge lines between the pads, and removing the exposed bridge lines.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: June 10, 2008
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Hung-Nan Chen, Jen-Kuang Fang, Kuang-Lin Lo
  • Patent number: 7375020
    Abstract: The present invention provides a method of forming a plurality of bumps over a wafer. The wafer has a plurality of contact pads and a passivation layer thereon and the passivation layer exposes the contact pads. An adhesion layer is formed over the active surface of the wafer and covers both the contact pads and the passivation layer. A metallic layer is formed over the adhesion layer. The patterned adhesion layer and patterned metallic layer remain on top of the contact pads. A photoresist layer having a plurality of openings that expose the metallic layer is formed on the active surface of the wafer. A flux material is deposited into the openings and then a solder block is disposed into each of the openings. A reflow process is performed to bond the solder block with the metallic layer. Finally, the flux material and the photoresist layer are removed.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: May 20, 2008
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Hua Wu, Min-Lung Huang, Shih-Chang Lee, Jen-Kuang Fang, Yung-I Yeh
  • Patent number: 7262497
    Abstract: A bumpless assembly package mainly comprises a substrate, and a chip. The substrate has an upper surface and an opposite lower surface, a plurality of first contacts and a plurality of second contacts formed on the upper surface of the substrate, wherein one of the first contacts is electrically connected to one of the second contacts. The chip has an active surface and a boding pad formed on the active surface and is disposed in the opening, Moreover, an electrically conductive layer is disposed above the upper surface of the substrate and the active surface of the chip, and extended from the upper surface of the substrate to the active surface of the chip so as to electrically connect the chip and the substrate. In addition, a protective layer is provided to dispose above the electrically conductive layer and expose the second contacts so that the second contacts can electrically connect to external electronic devices.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: August 28, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Jen-Kuang Fang
  • Publication number: 20070166879
    Abstract: A multi-chip stack package includes a substrate, a first chip, a second chip, a plurality of bumps, a plurality ofjunction interface bumps, a plurality of conductive wires, a filler material and an encapsulating material. The substrate has a plurality of first contacts and a plurality of second contacts thereon. The first chip is bonded to the substrate surface by the bumps positioned between the active surface of the first chip and the first contacts. The second chip is bonded to the first chip by the junction interface bumps positioned between the back surface of the first chip and the back surface of the second chip. The conductive wires electrically connect the active surface of the second chip and the second contacts. The filler material encloses the bumps and the junction interface bumps. The encapsulating material encloses the first chip, the second chip and the conductive wires.
    Type: Application
    Filed: March 21, 2007
    Publication date: July 19, 2007
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Jen-Kuang Fang
  • Patent number: 7064428
    Abstract: A wafer-level package structure, applicable to a flip-chip arrangement on a carrier, which comprises a plurality of contact points, is described. This wafer-level package structure is mainly formed with a chip and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The conductive layer can further be arranged at a region outside the bonding pads on the chip as a heat sink to enhance the heat dissipation ability of the package.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: June 20, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
  • Publication number: 20060124703
    Abstract: A method of forming pre-solders on a substrate is provided. Firstly, a substrate is provided. The substrate includes an upper surface and a lower surface. There are several metal circuits and a solder mask both on the upper and the lower surfaces. Each solder mask covers parts of the corresponding metal circuits and parts of the corresponding surface for exposing parts of several pads of the corresponding metal circuits. Then, a patterned photo-resist film is formed on the upper surface. The patterned photo-resist film has several openings for exposing the upper-surface pads. Afterwards, several metal materials are formed in the opening by printing. Thereon, the metal materials are reflown to form several pre-solders on the upper-surface pads. Finally, the patterned photo-resist film is removed.
    Type: Application
    Filed: December 5, 2005
    Publication date: June 15, 2006
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jen-Kuang Fang, Chung-Hwa Feng