Patents by Inventor Jeng-Shyan Lin

Jeng-Shyan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170263659
    Abstract: An image-sensor device is provided. The image-sensor device includes a semiconductor substrate and a radiation-sensing region in the semiconductor substrate. The image-sensor device also includes a doped isolation region adjacent to the radiation-sensing region. The image-sensor device further includes a dielectric film extending into the doped isolation region from a surface of the semiconductor substrate. A portion of the doped isolation region is between the dielectric film and the radiation-sensing region.
    Type: Application
    Filed: May 26, 2017
    Publication date: September 14, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jeng-Shyan LIN, Dun-Nian YAUNG, Jen-Cheng LIU, Feng-Chi HUNG
  • Patent number: 9761629
    Abstract: A system and method for reducing cross-talk between photosensitive diodes is provided. In an embodiment a first color filter is formed over a first photosensitive diode and a second color filter is formed over a second photosensitive diode, and a gap is formed between the first color filter and the second color filter. The gap will serve to reflect light that otherwise would have crossed from the first color filter to the second color filter, thereby reducing cross-talk between the first photosensitive diode and the second photosensitive diode. A reflective grid may also be formed between the first photosensitive diode and the second photosensitive diode in order to assist in the reflection and further reduce the amount of cross-talk.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: September 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Jeng-Shyan Lin, Shuang-Ji Tsai
  • Publication number: 20170250215
    Abstract: An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.
    Type: Application
    Filed: May 15, 2017
    Publication date: August 31, 2017
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Shuang-Ji Tsai, Yueh-Chiou Lin
  • Patent number: 9748304
    Abstract: Image sensor devices, methods of manufacture thereof, and semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes bonding a first semiconductor wafer to a second semiconductor wafer, the first semiconductor wafer comprising a substrate and an interconnect structure coupled to the substrate. The method includes removing a portion of the substrate from the first semiconductor wafer to expose a portion of the interconnect structure.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: U-Ting Chen, Shu-Ting Tsai, Szu-Ying Chen, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu
  • Publication number: 20170200697
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate has an active region. The semiconductor substrate is doped with first dopants with a first-type conductivity. The active region is adjacent to the first surface and doped with second dopants with a second-type conductivity. The semiconductor device structure includes a doped layer over the second surface and doped with third dopants with the first-type conductivity. A first doping concentration of the third dopants in the doped layer is greater than a second doping concentration of the first dopants in the semiconductor substrate. The semiconductor device structure includes a conductive bump over the doped layer.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 13, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Min-Feng KAO, Dun-Nian YAUNG, Jen-Cheng LIU, Jeng-Shyan LIN, Hsun-Ying HUANG
  • Patent number: 9699897
    Abstract: One or more techniques or systems for mitigating peeling associated with a pad, such as a pad of a semiconductor, are provided herein. In some embodiments, a pad structure for mitigating peeling comprises a bond region located above a first region. In some embodiments, a first inter-layer dielectric region associated with the first region is formed in an inter-layer region under the pad. Additionally, a first inter-metal dielectric region associated with the first region is formed in an inter-metal region under the inter-layer region. In some embodiments, the first inter-metal region is formed under the first inter-layer region. In this manner, peeling associated with the pad structure is mitigated, at least because the first inter-metal dielectric region comprises dielectric material and the first inter-layer dielectric region comprises dielectric material, thus forming a dielectric-dielectric interface between the first inter-metal dielectric region and the inter-layer dielectric region.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Szu-Ying Chen, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Chia-Wei Liu, Chung-Chuan Tseng
  • Publication number: 20170186799
    Abstract: The present disclosure relates to a method of forming a multi-dimensional integrated chip having tiers connected in a front-to-back configuration, and an associated apparatus. In some embodiments, the method is performed by forming one or more semiconductor devices within a first substrate, forming one or more image sensing elements within a second substrate, and bonding a first dielectric structure over the first substrate to a back-side of the second substrate by way of a bonding structure. An inter-tier interconnect structure, comprising a plurality of different segments, respectively having sidewalls with different sidewall angles, is formed to extend through the bonding structure and the second substrate. The inter-tier interconnect structure is configured to electrically couple a first metal interconnect layer over the first substrate to a second metal interconnect layer over the second substrate.
    Type: Application
    Filed: November 30, 2016
    Publication date: June 29, 2017
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang, Wei-Chih Weng, Yu-Yang Shen
  • Publication number: 20170186796
    Abstract: A frontside illuminated (FSI) image sensor with a reflector is provided. A photodetector is buried in a sensor substrate. A support substrate is arranged under and bonded to the sensor substrate. The reflector is arranged under the photodetector, between the sensor and support substrates, and is configured to reflect incident radiation towards the photodetector. A method for manufacturing the FSI image sensor and the reflector is also provided.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 29, 2017
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Jeng-Shyan Lin, Hsun-Ying Huang, Tzu-Hsuan Hsu
  • Patent number: 9666624
    Abstract: An image-sensor device is provided. The image-sensor device includes a semiconductor substrate having a front surface and a back surface, and an interconnection structure formed over the front surface. The image-sensor device also includes a radiation-sensing region in the semiconductor substrate. The image-sensor device further includes an isolation structure adjacent to the radiation-sensing region. The isolation structure includes a trench extends from the back surface, and a negatively charged film extends along an interior surface of the trench.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung
  • Patent number: 9653508
    Abstract: An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Shuang-Ji Tsai, Yueh-Chiou Lin
  • Publication number: 20170125341
    Abstract: An integrated circuit structure with a back side through silicon via (B/S TSV) therein and a method of forming the same is disclosed. The method includes the steps of: receiving a wafer comprising a substrate having a front side that has a conductor thereon and a back side; forming a back side through silicon via (B/S TSV) from the back side of the substrate to penetrate the substrate; and filling the back side through silicon via (B/S TSV) with a conductive material to form an electrical connection with the conductor. Thus a back side through silicon via penetrates the back side of the substrate and electrically connects to the conductor on the front side of the substrate is formed.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: Jeng-Shyan LIN, Dun-Nian YAUNG, Hsing-Chih LIN, Jen-Cheng LIU, Min-Feng KAO, Hsun-Ying HUANG
  • Publication number: 20170117316
    Abstract: The present disclosure relates to an integrated circuit having a bond pad with a relatively flat surface topography that mitigates damage to underlying layers. In some embodiments, the integrated circuit has a plurality of metal interconnect layers within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has a recess with sidewalls connecting a horizontal surface of the passivation structure to an upper surface of the passivation structure. A bond pad is arranged within the recess and has a lower surface overlying the horizontal surface. One or more protrusions extend outward from the lower surface through openings in the passivation structure to contact one of the metal interconnect layers. Arranging the bond pad within the recess and over the passivation structure mitigates stress to underlying layers during bonding without negatively impacting an efficiency of an image sensing element within the substrate.
    Type: Application
    Filed: May 9, 2016
    Publication date: April 27, 2017
    Inventors: Kai-Chun Hsu, Ching-Chun Wang, Dun-Nian Yaung, Jeng-Shyan Lin, Shyh-Fann Ting
  • Publication number: 20170110496
    Abstract: An apparatus comprises a first semiconductor chip including a first substrate, a plurality of first inter-metal dielectric layers and a plurality of first metal lines, a second semiconductor chip having a surface in contact with a surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second inter-metal dielectric layers and a plurality of second metal lines and a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion over a first side of a hard mask layer and a second portion over a second side of the hard mask layer, wherein the hard mask layer is a ring-shaped layer, and wherein the conductive plug is formed in a center opening of the ring-shaped layer.
    Type: Application
    Filed: December 30, 2016
    Publication date: April 20, 2017
    Inventors: Jeng-Shyan Lin, Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Shih Pei Chou, Min-Feng Kao, Szu-Ying Chen
  • Patent number: 9627430
    Abstract: A method and apparatus for a low resistance image sensor contact, the apparatus comprising a photosensor disposed in a substrate, a first ground well disposed in a first region of the substrate, the first ground well having a resistance lower than the substrate, and a ground line disposed in a region adjacent to the first ground well. The first ground well is configured to provide a low resistance path to the ground line from the substrate for excess free carriers in the first region of the substrate. The apparatus may optionally comprise a second ground well having a lower resistance than the first ground well and disposed between the first ground well and the ground line, and may further optionally comprise a third ground well having a lower resistance than the second ground well and disposed between the second ground well and the ground line.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chun-Chieh Chuang, Shuang-Ji Tsai, Jeng-Shyan Lin
  • Publication number: 20170098679
    Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.
    Type: Application
    Filed: December 19, 2016
    Publication date: April 6, 2017
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shuang-Ji Tsai, Jeng-Shyan Lin, Shu-Ting Tsai, Wen-I Hsu
  • Patent number: 9543257
    Abstract: An interconnect device and a method of forming the interconnect device are provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. One or more dielectric films are formed along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits, while using some of the pads as hard masks. The first opening and the second opening are filled with a conductive material to form a conductive plug.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung
  • Publication number: 20170005076
    Abstract: An integrated circuit structure includes a first and a second semiconductor chip. The first semiconductor chip includes a first substrate and a first plurality of dielectric layers underlying the first substrate. The second semiconductor chip includes a second substrate and a second plurality of dielectric layers over the second substrate, wherein the first and the second plurality of dielectric layers are bonded to each other. A metal pad is in the second plurality of dielectric layers. A redistribution line is over the first substrate. A conductive plug is electrically coupled to the redistribution line. The conductive plug includes a first portion extending from a top surface of the first substrate to a bottom surface of the first substrate, and a second portion extending from the bottom surface of the first substrate to the metal pad. A bottom surface of the second portion contacts a top surface of the metal pad.
    Type: Application
    Filed: September 19, 2016
    Publication date: January 5, 2017
    Inventors: Cheng-Ying Ho, Jeng-Shyan Lin, Wen-I Hsu, Feng-Chi Hung, Dun-Nian Yaung, Ying-Ling Tsai
  • Patent number: 9536777
    Abstract: A method comprises bonding a first chip on a second chip, depositing a first hard mask layer over a non-bonding side of the first chip, depositing a second hard mask layer over the first hard mask layer, etching a first substrate of the first semiconductor chip using the second hard mask layer as a first etching mask and etching the IMD layers of the first chip and the second chip using the first hard mask layer as a second etching mask.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacutring Company, Ltd.
    Inventors: Jeng-Shyan Lin, Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Shih Pei Chou, Min-Feng Kao, Szu-Ying Chen
  • Publication number: 20160379963
    Abstract: A stacked semiconductor device and a method of forming the stacked semiconductor device are provided. A plurality of integrated circuits are bonded to one another to form the stacked semiconductor device. After each bonding step to bond an additional integrated circuit to a stacked semiconductor device formed at the previous bonding step, a plurality of conductive plugs are formed to electrically interconnect the additional integrated circuit to the stacked semiconductor device formed at the previous bonding step.
    Type: Application
    Filed: September 6, 2016
    Publication date: December 29, 2016
    Inventors: Shu-Ting Tsai, Szu-Ying Chen, Jeng-Shyan Lin, Tzu-Hsuan Hsu, Feng-Chi Hung, Dun-Nian Yaung
  • Patent number: 9525003
    Abstract: The present disclosure provides a device having a doped active region disposed in a substrate. The doped active region having an elongate shape and extends in a first direction. The device also includes a plurality of first metal gates disposed over the active region such that the first metal gates each extend in a second direction different from the first direction. The plurality of first metal gates includes an outer-most first metal gate having a greater dimension measured in the second direction than the rest of the first metal gates. The device further includes a plurality of second metal gates disposed over the substrate but not over the doped active region. The second metal gates contain different materials than the first metal gates. The second metal gates each extend in the second direction and form a plurality of respective N/P boundaries with the first metal gates.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: December 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shuang-Ji Tsai, Jeng-Shyan Lin, Shu-Ting Tsai, Wen-I Hsu