Patents by Inventor Jenn-Hwa Huang

Jenn-Hwa Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10355085
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a semiconductor layer, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 16, 2019
    Assignee: NXP USA, Inc.
    Inventors: Jenn Hwa Huang, Yuanzheng Yue
  • Publication number: 20190206994
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a semiconductor layer, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Jenn Hwa Huang, Yuanzheng Yue
  • Publication number: 20190206998
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a channel, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Jenn Hwa Huang, Yuanzheng Yue
  • Publication number: 20190198623
    Abstract: A semiconductor device includes a base substrate, a doped region at an upper surface of the base substrate, and a transistor over the upper surface of the base substrate and formed from a plurality of epitaxially-grown semiconductor layers. The doped region includes one or more ion species, and has a lower boundary above a lower surface of the base substrate. The base substrate may be a silicon substrate, and the transistor may be a GaN HEMT formed from a plurality of heteroepitaxial layers that include aluminum nitride and/or aluminum gallium nitride. The doped region may be a diffusion barrier region and/or an enhanced resistivity region. The ion species may be selected from phosphorus, arsenic, antimony, bismuth, argon, helium, nitrogen, and oxygen. When the ion species includes oxygen, the doped region may include a silicon dioxide layer formed from annealing the doped region after introduction of the oxygen.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Inventors: Yuanzheng Yue, David Cobb Burdeaux, Jenn Hwa Huang, Bruce McRae Green, James Allen Teplik
  • Publication number: 20190157440
    Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with a contact region formed within the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.
    Type: Application
    Filed: December 31, 2018
    Publication date: May 23, 2019
    Inventors: Bruce McRae Green, Darrell Glenn Hill, Karen Elizabeth Moore, Jenn-Hwa Huang, Yuanzheng Yue, James Allen Teplik, Lawrence Scott Klingbeil
  • Patent number: 9972703
    Abstract: Transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode (102). The field plate (108) and charged dielectric layer (106) provide the ability to modulate the electric field or capacitance in the transistor. For example, the charged dielectric layer (106) provides the ability to control the capacitance between the gate electrode (102) and field plate (108). Modulating such capacitances or the electric field in transistors can facilitate improved performance. For example, controlling gate electrode (102) to field plate (108) capacitance can be used to improve device linearity and/or breakdown voltage. Such control over gate electrode (102) to field plate (108) capacitance or electric fields provides for high speed and/or high voltage transistor operation.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: May 15, 2018
    Assignee: NXP USA, INC.
    Inventors: Jenn Hwa Huang, James A. Teplik
  • Patent number: 9893156
    Abstract: A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: February 13, 2018
    Assignee: NXP USA, INC.
    Inventors: Jenn Hwa Huang, Tianwei Sun, James A. Teplik
  • Patent number: 9871107
    Abstract: An embodiment of a device includes a semiconductor substrate, a transistor formed at the first substrate surface, a first conductive feature formed over the first substrate surface and electrically coupled to the transistor, and a second conductive feature covering only a portion of the second substrate surface to define a first conductor-less region. A cavity vertically aligned with the first conductive feature within the first conductor-less region extends into the semiconductor substrate. A dielectric medium may be disposed within the cavity and have a dielectric constant less than a dielectric constant of the semiconductor substrate. A method for forming the device may include forming a semiconductor substrate, forming a transistor on the semiconductor substrate, forming the first conductive feature, forming the second conductive feature, forming the conductor-less region, forming the cavity, and filling the cavity with the dielectric medium.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: January 16, 2018
    Assignee: NXP USA, INC.
    Inventors: Bruce M. Green, Jenn Hwa Huang, Vikas S. Shilimkar
  • Patent number: 9799760
    Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: October 24, 2017
    Assignee: NXP USA, INC.
    Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
  • Publication number: 20170200794
    Abstract: A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.
    Type: Application
    Filed: March 28, 2017
    Publication date: July 13, 2017
    Inventors: JENN HWA HUANG, TIANWEI SUN, JAMES A. TEPLIK
  • Publication number: 20170141190
    Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11, 13) with one or more device mesas (41) in which isolation regions (92, 93) are formed using an implant mask (81) to implant ions (91) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode (111) from contacting the peripheral edge and sidewalls of the mesa structures.
    Type: Application
    Filed: February 1, 2017
    Publication date: May 18, 2017
    Inventors: Jenn Hwa Huang, Weixiao Huang
  • Patent number: 9647075
    Abstract: A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: May 9, 2017
    Assignee: NXP USA, INC.
    Inventors: Jenn Hwa Huang, Tianwei Sun, James A. Teplik
  • Patent number: 9601638
    Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11, 13) with one or more device mesas (41) in which isolation regions (92, 93) are formed using an implant mask (81) to implant ions (91) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode (111) from contacting the peripheral edge and sidewalls of the mesa structures.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: March 21, 2017
    Assignee: NXP USA, INC.
    Inventors: Jenn Hwa Huang, Weixiao Huang
  • Publication number: 20170077245
    Abstract: A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.
    Type: Application
    Filed: September 16, 2015
    Publication date: March 16, 2017
    Inventors: Jenn Hwa Huang, Tianwei Sun, James A. Teplik
  • Publication number: 20160343833
    Abstract: Transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode (102). The field plate (108) and charged dielectric layer (106) provide the ability to modulate the electric field or capacitance in the transistor. For example, the charged dielectric layer (106) provides the ability to control the capacitance between the gate electrode (102) and field plate (108). Modulating such capacitances or the electric field in transistors can facilitate improved performance. For example, controlling gate electrode (102) to field plate (108) capacitance can be used to improve device linearity and/or breakdown voltage. Such control over gate electrode (102) to field plate (108) capacitance or electric fields provides for high speed and/or high voltage transistor operation.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 24, 2016
    Inventors: Jenn Hwa Huang, James A. Teplik
  • Publication number: 20160343809
    Abstract: An embodiment of a device includes a semiconductor substrate, a transistor formed at the first substrate surface, a first conductive feature formed over the first substrate surface and electrically coupled to the transistor, and a second conductive feature covering only a portion of the second substrate surface to define a first conductor-less region. A cavity vertically aligned with the first conductive feature within the first conductor-less region extends into the semiconductor substrate. A dielectric medium may be disposed within the cavity and have a dielectric constant less than a dielectric constant of the semiconductor substrate. A method for forming the device may include forming a semiconductor substrate, forming a transistor on the semiconductor substrate, forming the first conductive feature, forming the second conductive feature, forming the conductor-less region, forming the cavity, and filling the cavity with the dielectric medium.
    Type: Application
    Filed: May 22, 2015
    Publication date: November 24, 2016
    Inventors: BRUCE M. GREEN, JENN HWA HUANG, VIKAS S. SHILIMKAR
  • Patent number: 9425267
    Abstract: Transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode (102). The field plate (108) and charged dielectric layer (106) provide the ability to modulate the electric field or capacitance in the transistor. For example, the charged dielectric layer (106) provides the ability to control the capacitance between the gate electrode (102) and field plate (108). Modulating such capacitances or the electric field in transistors can facilitate improved performance. For example, controlling gate electrode (102) to field plate (108) capacitance can be used to improve device linearity and/or breakdown voltage. Such control over gate electrode (102) to field plate (108) capacitance or electric fields provides for high speed and/or high voltage transistor operation.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 23, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jenn Hwa Huang, James A. Teplik
  • Publication number: 20150357452
    Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.
    Type: Application
    Filed: August 17, 2015
    Publication date: December 10, 2015
    Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
  • Patent number: 9153448
    Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: October 6, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
  • Patent number: 9111868
    Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: August 18, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore