Abstract: A vertical FET is fabricated by etching through a contact layer into a drift layer on a compound semiconductor substrate to form a plurality of mesas, each mesa having an upper surface and each adjacent pair of mesas defining therebetween a trench with sidewalls and a bottom. A conductive layer is conformally deposited over the plurality of mesas and the trenches and anisotropically etched to form contacts on the sidewalls of the trenches and depositing source contacts on the upper surfaces of the mesas and a drain contact on a reverse side of the substrate.

Abstract: A multi-state non-volatile ferroelectric memory includes a field effect transistor having a gate insulator formed of ferroelectric material. The ferroelectric material is separated into regions of different characteristics, e.g. different thicknesses, different coercive field values, etc., so as to provide a plurality of different threshold voltages for the field effect transistor.

Abstract: A semiconductor device includes a buffer layer (23) having a doped region (24), a barrier layer (26) over the buffer layer (23) and having a doped region (27), and a channel layer (25) located between the buffer layer (23) and the barrier layer (26) where the doping density of the doped region (27) in the barrier layer (26) is higher than the doping densities of the channel layer (25) and the doped region (24) in the first buffer layer (23).

Abstract: A method of passivating semiconductor devices including the steps of providing a semiconductor device having a surface of semiconductor material to be passivated, exposing the surface of semiconductor material to deep ultra-violet (DUV) radiation in an ambiance including oxygen so as to form a layer of oxide on the surface of semiconductor material, and forming a layer of passivation material on the layer of oxide. The DUV oxide forms a different interface with the semiconductor material which significantly improves operating characteristics of the semiconductor device.

Abstract: A high power heterojunction field effect transistor comprising a first barrier layer including a semiconductor material having a band gap, a second barrier layer including a semiconductor material having a band gap, a channel layer including a semiconductor material having a band gap narrower than the band gaps of the material included in the first barrier layer and the second barrier layer and sandwiched therebetween and an interface layer sandwiched between the channel layer and the first barrier layer.

Abstract: A semiconductor device including a plurality of layers of material defining a diffusion barrier. A defect generator positioned on the plurality of layers in overlying relationship to the diffusion barrier so as to produce a collection of defects at the diffusion barrier that operates as a current restriction. In a typical example, an ohmic contact is positioned around the mesa of a ridge VCSEL, which ohmic contact generates defects that accumulate at a hetero-interface near the active area and confine the current flow to a lasing volume of the VCSEL.

Abstract: A stable FET including a substrate structure with a doped layer formed as a portion of the substrate structure and defining an electrically conductive shielding region adjacent a surface of the substrate structure. A channel region is positioned on the shielding region and includes a plurality of epitaxial layers grown on the surface of the substrate structure in overlying relationship to the doped layer. A drain and a source are positioned on the channel region in spaced relationship from each other with a gate positioned in overlying relationship on the channel region between the drain and source. An externally accessible electrical contact is connected to the shielding region and to the source region to provide a path for the removal of internally generated charges, such as holes.

Abstract: A heterostructure field effect transistor and method including at least one passivation layer (20) and at least one etch stop layer (22). Enhancement, depletion and combined devices with both enhancement mode and depletion mode devices are possible with minor process variations. Refractory gate (40) and non-gold refractory ohmic contact (52) metallization combined with other features allows non-liftoff metal patterning.

Abstract: A method of fabricating semiconductor devices with a passivated surface includes providing first cap and etch stop layers and second cap and etch stop layers with a contact layer thereon so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually etched to define an electrode contact area and to expose the inter-electrode surface area. Portions of the first etch stop and cap layers remaining in the contact area are selectively removed and a metal contact is formed in the contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.

Abstract: A method of fabricating semiconductor devices with a passivated surface includes providing a contact layer on a substrate so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other and to the substrate and the contact layer, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually and selectively etched to define an electrode contact area and to expose the inter-electrode surface area. The exposed inter-electrode surface area is passivated, either subsequent to or during the etching of the first layer. A metal contact is formed in the electrode contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.

Abstract: A method of fabricating buried control elements in a semiconductor device by providing a substrate and forming an epitaxial layer on the substrate. A native oxide is formed on the surface, and a mask is then positioned adjacent the surface so as to define a growth area and an unmasked portion. A bright light is selectively directed to grow an oxide film on the unmasked portion of the surface. After forming the oxide film, the native oxide on the growth area is desorbed and a buried control element layer is grown on the epitaxial layer. Subsequently, the oxide film is desorbed and the epitaxial layer is regrown, thereby burying the buried control element layer.

Abstract: A complementary III-V heterostructure field effect device includes the same refractory ohmic material for providing the contacts (117, 119), to both the N-type and P-type devices. Furthermore, the refractory ohmic contacts (117, 119) directly contact the InGaAs channel layer (16) to provide improved ohmic contact, despite the fact that the structure incorporates an advantageous high aluminum composition barrier layer (18) and an advantageous GaAs cap layer (20).

Abstract: The present invention encompasses a complementary semiconductor device having the same type of material providing the ohmic contacts (117, 119) to both the N-type and P-type devices. In a preferred embodiment, P-source and P -drain regions ( 80, 82 ) are heavily doped with a P-type impurity (81, 83) so that an ohmic with N-type impurity can be used as an ohmic contact. One ohmic material that may be used is nickel-germanium-tungsten. Nickel-germanium-tungsten is etchable, and therefore does not require lift-off processing. Furthermore, a preferred complementary semiconductor device made in accordance with the present invention is compatible with modern aluminum based VLSI interconnection processes.

Abstract: The present invention encompasses a method for providing the same ohmic material contact (120, 122, 124) to N-type and P-type regions (70, 80) of a III-V semiconductor device. Specifically, an N-type region (70) extending through a semiconductor structure is formed. Additionally, a P-type region (80) extending through the substrate is formed. The P-type region (80) may be heavily doped with P-type impurities (81). A first ohmic region (117) is formed, contacting the N-type region (70). The first ohmic region may comprise an ohmic material including metal and an N-type dopant. A second ohmic region (119) is formed, contacting the P-type region (80, 81). The second ohmic region comprises the same ohmic material as the first ohmic region. One ohmic material that may be used is nickel-germanium-tungsten.

Abstract: Self-aligned HFETS are fabricated by providing a semi-insulating substrate and forming a low bandgap III-V semiconductor layer thereon. A first dielectric layer of a first dielectric material is formed on the III-V layer and first and second openings are formed through the first dielectric layer and the III-V layer. After forming dielectric spacers of a second dielectric material on the sidewalls of the first and second openings, gates are formed therein. The first dielectric layer is subsequently removed and source and drain regions are formed in the III-V layer and substrate adjacent to each of the gates. The formation of the source and drain regions is self-aligned to the gates. After forming isolation regions between devices, ohmic contacts to the source and drain regions, all being of a like material, are formed. This formation is also self-aligned to the gates.

Abstract: A method of fabricating heterojunction structures includes providing a semiconductor substrate and forming a plurality of semiconductor layers thereon. Ohmic and gate contacts are then formed on the plurality of semiconductor layers and portions of at least one of the semiconductor layers disposed between the ohmic and gate contacts are removed. Gate metal is then formed on the gate contacts. Source and drain regions are formed in the semiconductor layers and the formation is self-aligned to the gate metal. Following the formation of the source and drain regions, ohmic metal is formed on the ohmic contacts.

Abstract: A GaAs complementary HFET structure having an anisotype layer formed underneath the P-channel device gate is provided. The anisotype layer is heavily doped N-type and is formed in contact with a semi-insulating AlGaAs barrier of the P-channel FET. A pre-ohmic layer is formed over the anisotype layer and a gate electrode is formed over the pre-ohmic layer. In a first embodiment, the pre-ohmic layer comprises undoped gallium arsenide amd the gate electrode forms a Schottky diode with the pre-ohmic layer. The anisotype layer forms a semiconductor junction with the semi-insulating AlGaAs barrier wherein the semiconductor junction replaces or augments a conventional Schottky junction. In a second embodiment, the pre-ohmic layer comprises heavily doped InGaAs and the gate electrode forms an ohmic contact to the doped InGaAs. The semiconductor junction at the P-channel device gate results in higher built in potential barrier and improved P-channel gate turn on voltage.

Abstract: A heterojunction bipolar transistor having a planar surface topology, reduced lateral dimensions and a base electrode aligned to both the emitter and collector electrodes is fabricated by forming sub-collector, collector, base and one or more emitter layers on a substrate. An opening extending to the sub-collector layer is then formed and a first portion of the collector electrode is formed therein so that the sidewalls of the opening are not contacted by the first portion. Dielectric material is then formed between the sidewalls of the opening and the first portion of the collector electrode. A second portion of the collector electrode is then formed on the first portion of the collector electrode along with an emitter electrode so that the second portion of the collector electrode and the emitter electrode are substantially planar. After then exposing the base layer, the self-aligned base electrode is formed between the second portion of the collector electrode and the emitter electrode.