Patents by Inventor Jennifer Wong

Jennifer Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160187324
    Abstract: Antibody/signal-generating moiety conjugates are disclosed that include an antibody covalently linked to a signal-generating moiety through a heterobifunctional polyalkyleneglycol linker. The disclosed conjugates show exceptional signal-generation in immunohistochemical and in situ hybridization assays on tissue sections and cytology samples. In one embodiment, enzyme-metallographic detection of nucleic acid sequences with hapten-labeled probes can be accomplished using the disclosed conjugates as a primary antibody without amplification.
    Type: Application
    Filed: March 9, 2016
    Publication date: June 30, 2016
    Inventors: Christopher Bieniarz, Jerome W. Kosmeder, Mark Lefever, Casey A. Kernag, Julia Ashworth-Sharpe, Jennifer Wong
  • Patent number: 9315789
    Abstract: Antibody/signal-generating moiety conjugates are disclosed that include an antibody covalently linked to a signal-generating moiety through a heterobifunctional polyalkyleneglycol linker. The disclosed conjugates show exceptional signal-generation in immunohistochemical and in situ hybridization assays on tissue sections and cytology samples. In one embodiment, enzyme-metallographic detection of nucleic acid sequences with hapten-labeled probes can be accomplished using the disclosed conjugates as a primary antibody without amplification.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: April 19, 2016
    Assignee: Ventana Medical Systems, Inc.
    Inventors: Christopher Bieniarz, Jennifer Wong, Mark Lefever, Jerome W. Kosmeder, II, Julia Ashworth-Sharpe, Casey A. Kernag
  • Publication number: 20140147906
    Abstract: Antibody/signal-generating moiety conjugates are disclosed that include an antibody covalently linked to a signal-generating moiety through a heterobifunctional polyalkyleneglycol linker. The disclosed conjugates show exceptional signal-generation in immunohistochemical and in situ hybridization assays on tissue sections and cytology samples. In one embodiment, enzyme-metallographic detection of nucleic acid sequences with hapten-labeled probes can be accomplished using the disclosed conjugates as a primary antibody without amplification.
    Type: Application
    Filed: January 2, 2014
    Publication date: May 29, 2014
    Applicant: Ventana Medical Systems, Inc.
    Inventors: Christopher Bieniarz, Jennifer Wong, Mark Lefever, Jerome W. Kosmeder, II, Julia Ashworth-Sharpe, Casey A. Kernag
  • Patent number: 8658389
    Abstract: Antibody/signal-generating moiety conjugates are disclosed that include an antibody covalently linked to a signal-generating moiety through a heterobifunctional polyalkyleneglycol linker. The disclosed conjugates show exceptional signal-generation in immunohistochemical and in situ hybridization assays on tissue sections and cytology samples. In one embodiment, enzyme-metallographic detection of nucleic acid sequences with hapten-labeled probes can be accomplished using the disclosed conjugates as a primary antibody without amplification.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: February 25, 2014
    Assignee: Ventana Medical Systems, Inc.
    Inventors: Christopher Bieniarz, Jennifer Wong, Mark Lefever, Jerome W. Kosmeder, II, Julia Ashworth-Sharpe, Casey A. Kernag
  • Patent number: 8495122
    Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each slice includes a mode port that receives mode control signals for dynamically altering the function and connectivity of related slices. Such alterations can occur with or without reconfiguring the PLD.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: July 23, 2013
    Assignee: Xilinx, Inc.
    Inventors: James M. Simkins, Steven P. Young, Jennifer Wong, Bernard J. New, Alvin Y. Ching
  • Patent number: 7882165
    Abstract: A digital signal processing circuit including: a multiplier circuit; a plurality of multiplexers coupled to the multiplier circuit and controlled by a first opcode; and an arithmetic logic unit coupled to plurality of multiplexers and controlled by a second opcode.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: February 1, 2011
    Assignee: Xilinx, Inc.
    Inventors: James M. Simkins, Jennifer Wong, Bernard J. New, Alvin Y. Ching, John M. Thendean, Anna Wing Wah Wong, Vasisht Mantra Vadi, David P. Schultz
  • Patent number: 7870182
    Abstract: An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, where the second adder is coupled to a second opcode register.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: January 11, 2011
    Assignee: Xilinx Inc.
    Inventors: John M. Thendean, Jennifer Wong, Bernard J. New, Alvin Y. Ching, James M. Simkins, Anna Wing Wah Wong, Vasisht Mantra Vadi
  • Patent number: 7865542
    Abstract: A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: January 4, 2011
    Assignee: Xilinx, Inc.
    Inventors: Bernard J. New, Vasisht Mantra Vadi, Jennifer Wong, Alvin Y. Ching, John M. Thendean, Anna Wing Wah Wong, James M. Simkins
  • Patent number: 7860915
    Abstract: A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with the inverted pattern to produce a second output; bitwise masking the first and second outputs using a mask of a plurality of masks to produce third and fourth output bits; combining the third and fourth output bits to produce first and a second output comparison bits; and storing the first and second output comparison bits in a memory.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: December 28, 2010
    Assignee: Xilinx, Inc.
    Inventors: Vasisht Mantra Vadi, Jennifer Wong, Bernard J. New, Alvin Y. Ching, John M. Thendean, Anna Wing Wah Wong, James M. Simkins
  • Patent number: 7853636
    Abstract: An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for rounding the summation based at least in part on the comparison bit.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: December 14, 2010
    Assignee: Xilinx, Inc.
    Inventors: Bernard J. New, Jennifer Wong, James M. Simkins, Alvin Y. Ching, John M. Thendean, Anna Wing Wah Wong, Vasisht Mantra Vadi
  • Patent number: 7853634
    Abstract: An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: December 14, 2010
    Assignee: Xilinx, Inc.
    Inventors: James M. Simkins, Jennifer Wong, Bernard J. New, Alvin Y. Ching, John M. Thendean, Anna Wing Wah Wong, Vasisht Mantra Vadi
  • Patent number: 7853632
    Abstract: A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: December 14, 2010
    Assignee: Xilinx, Inc.
    Inventors: Alvin Y. Ching, Jennifer Wong, Bernard J. New, James M. Simkins, John M. Thendean, Anna Wing Wah Wong, Vasisht Mantra Vadi
  • Patent number: 7849119
    Abstract: An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: December 7, 2010
    Assignee: Xilinx, Inc.
    Inventors: Vasisht Mantra Vadi, Jennifer Wong, Bernard J. New, Alvin Y. Ching, John M. Thendean, Anna Wing Wah Wong, James M. Simkins
  • Patent number: 7844653
    Abstract: A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and an arithmetic logic unit (ALU) having a second adder circuit and coupled to the set of multiplexers.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: November 30, 2010
    Assignee: Xilinx, Inc.
    Inventors: James M. Simkins, John M. Thendean, Vasisht Mantra Vadi, Bernard J. New, Jennifer Wong, Anna Wing Wah Wong, Alvin Y. Ching
  • Patent number: 7840627
    Abstract: An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: November 23, 2010
    Assignee: Xilinx, Inc.
    Inventors: James M. Simkins, Jennifer Wong, Bernard J. New, Alvin Y. Ching, John M. Thendean, Anna Wing Wah Wong, Vasisht Mantra Vadi
  • Patent number: D771072
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: November 8, 2016
    Assignee: Lutron Electronics Co., Inc.
    Inventors: Brent Protzman, Michelle L. Greene, Erica L. Clymer, Jennifer Wong, Laura Marie Friedlander, Joseph Roy Parks, Edward J. Blair
  • Patent number: D771102
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: November 8, 2016
    Assignee: Lutron Electronics Co., Inc.
    Inventors: Brent Protzman, Michelle L. Greene, Erica L. Clymer, Jennifer Wong, Samuel F. Chambers, Laura Marie Friedlander, Edward J. Blair, Stephen Lundy, John N. Callen
  • Patent number: D776151
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: January 10, 2017
    Assignee: Lutron Electronics Co., Inc.
    Inventors: Brent Protzman, Michelle L. Greene, Erica L. Clymer, Jennifer Wong, Laura Marie Friedlander, Joseph Roy Parks, John N. Callen
  • Patent number: D777199
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: January 24, 2017
    Assignee: Lutron Electronics Co., Inc.
    Inventors: Brent Protzman, Michelle L. Greene, Erica L. Clymer, Jennifer Wong, Stephen Lundy, Samuel F. Chambers
  • Patent number: D786924
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: May 16, 2017
    Assignee: Lutron Electronics Co., Inc.
    Inventors: Michelle L. Greene, Erica L. Clymer, Jennifer Wong, Laura Marie Friedlander