Abstract: A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided.

Abstract: A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided.

Abstract: A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided.

Abstract: A driver circuit (33) for output buffers or the like provides differing switching speed and di/dt depending on whether an output signal is switched in response to input signals or a control signal.

Abstract: A memory (20) has N.sub.BIAS generators (63 and 73) coupled to the positive and negative power supply lines (61 and 62) at a point close to amplifiers (84 and 85) and address buffers (76) to insure that they all receive the same power supply voltage to prevent an impact on the access times of memory (20). A V.sub.CS generator (65) is located close to power supply bonding pads (23 and 25) and to output buffers (77 and 78) to reduce the effects of power supply line noise on the noise margins. A V.sub.AREF generator provides a reference voltage to the differential amplifiers of address buffers (75 and 76). Locating V.sub.AREF generator (67) close to power supply bonding pads (23 and 25) insures that the reference voltage is always at the midpoint of the input logic swing.

Abstract: A regulated BiCMOS output buffer (34) regulates a logic high voltage of an output signal to improve interfacing to loads such as 3.3 volt integrated circuits. The output buffer (34) provides a first voltage to a base of a pullup transistor (116) in response to a difference between an input voltage and a reference voltage. An emitter of the pullup transistor (116) provides an output signal. A second transistor (102) having characteristics matching those of the pullup transistor (116) receives the first voltage at its base, and provides the input voltage at its emitter. The output buffer (34) changes the first voltage until the voltage at the base of the second transistor (102) equals the reference voltage. Thus, signal reflections on the output signal do not affect the performance of the output buffer. Clamps (99, 120) coupled to the base and emitter of the pullup transistor (116) provide soft clamping according to a square law.

Abstract: A parity SRAM having the capability to support byte parity is provided. The parity SRAM uses four (4) independent byte write enable (BWE.sub.x) signals to enable a write amplifier to individually write a single parity bit to a selected memory location. The SRAM is designed to function in either a parity or a non-parity mode. A bonding option pad is connected to parity control logic circuitry, and determines whether the SRAM will function in the parity mode or the non-parity mode. The parity control logic circuitry generates a parity signal, based on the electrical connection of the option pad. Thus, when the option pad is connected to ground, the parity option is selected, whereas, when the option pad is connected to a positive power supply, then non-parity functionality is selected. When parity functionality is selected, the the SRAM will allow the four (4) independent BWE.sub.x signals to individually enable the write amplifier.