Patents by Inventor Jens Peter Konrath

Jens Peter Konrath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11063142
    Abstract: A semiconductor device includes a silicon carbide body that includes a first section and a second section. The first section is adjacent to the second section. A drift region is formed in the first section and the second section. A lattice defect region is in a portion of the drift region in the second section. A first density of lattice defects, which include interstitials and vacancies in the lattice defect region, is at least double a second density of lattice defects, which include interstitials and vacancies in a portion of the drift region outside the lattice defect region.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 13, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Jens Peter Konrath, Wolfgang Bergner, Christian Hecht, Hans-Joachim Schulze, Andre Rainer Stegner
  • Patent number: 11024502
    Abstract: A method for forming a semiconductor device includes forming a mask layer with a first implantation window on a semiconductor substrate and implanting dopants with a first implantation energy into the semiconductor substrate through the first implantation window to form a first portion of a doping region of the semiconductor device. The mask layer is adapted to form a second implantation window of the mask layer. Further, dopants are implanted with a second implantation energy into the semiconductor substrate through the second implantation window. The second implantation energy differs from the first implantation energy and a lateral dimension of the first implantation window differs from a lateral dimension of the second implantation window.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: June 1, 2021
    Assignee: Infineon Technologies AG
    Inventors: Jens Peter Konrath, Jochen Hilsenbeck
  • Patent number: 10937784
    Abstract: A method for forming a semiconductor device includes: forming, in a silicon carbide layer of a first conductivity type having a first side, a first silicon carbide region and a second silicon carbide region that forms a pn-junction with the first silicon carbide region; forming a contact region that forms an Ohmic contact with the second silicon carbide region; forming a barrier-layer on the contact region and the first silicon carbide region so that a Schottky-junction is formed between the barrier-layer and the first silicon carbide region and so that an Ohmic connection is formed between the barrier-layer and the contact region, the barrier-layer comprising molybdenum nitride; and forming a first metallization on the barrier-layer, and in Ohmic connection with the barrier-layer.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: March 2, 2021
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Mihai Draghici, Jens Peter Konrath
  • Publication number: 20210050421
    Abstract: A silicon carbide device includes a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body. The gate structure has a gate length along a lateral first direction. A bottom surface and an active first gate sidewall of the gate structure are connected via a first bottom edge of the gate structure. The silicon carbide device further includes at least one source region of a first conductivity type. A shielding region of a second conductivity type is in contact with the first bottom edge of the gate structure across at least 20% of the gate length.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 18, 2021
    Inventors: Caspar Leendertz, Thomas Basler, Paul Ellinghaus, Rudolf Elpelt, Michael Hell, Jens Peter Konrath, Shiqin Niu, Dethard Peters, Konrad Schraml, Bernd Leonhard Zippelius
  • Publication number: 20210013320
    Abstract: A method of manufacturing a semiconductor device is proposed. A silicon carbide, SiC, semiconductor body is provided. Ions are introduced into the SiC semiconductor body through a first surface of the SiC semiconductor body by at least one ion implantation process. Thereafter, a SiC device layer is formed on the first surface of the SiC semiconductor body. Semiconductor device elements are formed in or over the SiC device layer.
    Type: Application
    Filed: July 10, 2020
    Publication date: January 14, 2021
    Inventors: Hans-Joachim Schulze, Jens Peter Konrath, Andre Rainer Stegner, Helmut Strack
  • Patent number: 10818749
    Abstract: A semiconductor device includes a plurality of drift regions of a plurality of field effect transistor structures arranged in a semiconductor substrate. The plurality of drift regions has a first conductivity type. The semiconductor device further includes a plurality of compensation regions arranged in the semiconductor substrate. The plurality of compensation regions has a second conductivity type. Each drift region of the plurality of drift regions is arranged adjacent to at least one compensation region of the plurality of compensation regions. The semiconductor device further includes a Schottky diode structure or metal-insulation-semiconductor gated diode structure arranged at the semiconductor substrate.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: October 27, 2020
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Wolfgang Bergner, Jens Peter Konrath, Dethard Peters, Reinhold Schoerner
  • Patent number: 10763339
    Abstract: A semiconductor device includes an n-doped monocrystalline semiconductor substrate having a substrate surface, an amorphous n-doped semiconductor surface layer at the substrate surface of the n-doped monocrystalline semiconductor substrate, and a Schottky-junction forming material in contact with the amorphous n-doped semiconductor surface layer. The Schottky-junction forming material forms at least one Schottky contact with the amorphous n-doped semiconductor surface layer.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: September 1, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Jens Peter Konrath, Ronny Kern, Stefan Krivec, Ulrich Schmid, Laura Stoeber
  • Publication number: 20200219972
    Abstract: A silicon carbide device includes a silicon carbide body including a source region of a first conductivity type, a cathode region of the first conductivity type and separation regions of a second conductivity type. A stripe-shaped gate structure extends along a first direction and adjoins the source region and the separation regions. The silicon carbide device includes a first load electrode. Along the first direction, the cathode region is between two separation regions of the separation regions and at least one separation region of the separation regions is between the cathode region and the source region. The source region and the first load electrode form an ohmic contact. The first load electrode and the cathode region form a Schottky contact.
    Type: Application
    Filed: January 3, 2020
    Publication date: July 9, 2020
    Inventors: Caspar LEENDERTZ, Rudolf ELPELT, Romain ESTEVE, Thomas GANNER, Jens Peter KONRATH, Larissa WEHRHAHN-KILIAN
  • Publication number: 20200203513
    Abstract: A semiconductor device includes a silicon carbide body that includes a first section and a second section. The first section is adjacent to the second section. A drift region is formed in the first section and the second section. A lattice defect region is in a portion of the drift region in the second section. A first density of lattice defects, which include interstitials and vacancies in the lattice defect region, is at least double a second density of lattice defects, which include interstitials and vacancies in a portion of the drift region outside the lattice defect region.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 25, 2020
    Inventors: Jens Peter KONRATH, Wolfgang BERGNER, Christian HECHT, Hans-Joachim SCHULZE, Andre Rainer STEGNER
  • Publication number: 20200194428
    Abstract: A method for forming a semiconductor device includes: forming, in a silicon carbide layer of a first conductivity type having a first side, a first silicon carbide region and a second silicon carbide region that forms a pn-junction with the first silicon carbide region; forming a contact region that forms an Ohmic contact with the second silicon carbide region; forming a barrier-layer on the contact region and the first silicon carbide region so that a Schottky-junction is formed between the barrier-layer and the first silicon carbide region and so that an Ohmic connection is formed between the barrier-layer and the contact region, the barrier-layer comprising molybdenum nitride; and forming a first metallization on the barrier-layer, and in Ohmic connection with the barrier-layer.
    Type: Application
    Filed: February 24, 2020
    Publication date: June 18, 2020
    Inventors: Ralf Siemieniec, Mihai Draghici, Jens Peter Konrath
  • Publication number: 20200185297
    Abstract: An embodiment of a semiconductor device includes a semiconductor body having a first main surface. The semiconductor body includes an active device area and an edge termination area at least partly surrounding the active device area. The semiconductor device further includes a contact electrode on the first main surface and electrically connected to the active device area. The semiconductor device further includes a passivation structure on the edge termination area and laterally extending into the active device area. The semiconductor device further includes an encapsulation structure on the passivation structure and covering a first edge of the passivation structure above the contact electrode.
    Type: Application
    Filed: December 3, 2019
    Publication date: June 11, 2020
    Inventors: Jens Peter Konrath, Jochen Hilsenbeck, Dethard Peters, Paul Salmen, Tobias Schmidutz, Vice Sodan, Christian Stahlhut, Juergen Steinbrenner, Bernd Zippelius
  • Patent number: 10672661
    Abstract: A semiconductor wafer having a main surface and a rear surface opposite from the main surface is provided. A die singulation preparation step is performed in kerf regions of the semiconductor wafer. The kerf regions enclose a plurality of die sites. The die singulation preparation step includes forming one or more preliminary kerf trenches between at least two immediately adjacent die sites. The method further includes forming active semiconductor devices in the die sites, and singulating the semiconductor wafer in the kerf regions thereby providing a plurality of discrete semiconductor dies from the die sites. The one or more preliminary kerf trenches are unfilled during the singulating, and the singulating includes removing semiconductor material from a surface of the semiconductor wafer that is between opposite facing sidewalls of the one or more preliminary kerf trenches.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 2, 2020
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Christian Westermeier, Jochen Hilsenbeck, Jens Peter Konrath, Boris Mayerhofer, Anatoly Sotnikov
  • Publication number: 20200135564
    Abstract: A semiconductor wafer having a main surface and a rear surface opposite from the main surface is provided. A die singulation preparation step is performed in kerf regions of the semiconductor wafer. The kerf regions enclose a plurality of die sites. The die singulation preparation step includes forming one or more preliminary kerf trenches between at least two immediately adjacent die sites. The method further includes forming active semiconductor devices in the die sites, and singulating the semiconductor wafer in the kerf regions thereby providing a plurality of discrete semiconductor dies from the die sites. The one or more preliminary kerf trenches are unfilled during the singulating, and the singulating includes removing semiconductor material from a surface of the semiconductor wafer that is between opposite facing sidewalls of the one or more preliminary kerf trenches.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Markus Zundel, Stefan Mieslinger, Thomas Ostermann, Christian Westermeier, Jochen Hilsenbeck, Jens Peter Konrath, Boris Mayerhofer, Anatoly Sotnikov
  • Patent number: 10593668
    Abstract: A semiconductor device includes a semiconductor body having a first silicon carbide region and a second silicon carbide region which forms a pn-junction with the first silicon carbide region, a first metallization on a front side of the semiconductor body, a contact region that forms an Ohmic contact with the second silicon carbide region, and a barrier-layer between the first metallization and the contact region and that is in Ohmic connection with the first metallization and the contact region. The barrier-layer forms a Schottky-junction with the first silicon carbide region, and includes molybdenum nitride or tantalum nitride. Additional semiconductor device embodiments and corresponding methods of manufacture are described.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: March 17, 2020
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Mihai Draghici, Jens Peter Konrath
  • Publication number: 20200066857
    Abstract: An embodiment of a semiconductor device comprises a SiC semiconductor body, a gate dielectric and a gate electrode. A first trench extends from a first surface of the SiC semiconductor body into the SiC semiconductor body. A junction material is in the first trench, wherein the junction material and the SiC semiconductor body form a diode.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 27, 2020
    Inventors: Jens Peter Konrath, Caspar Leendertz, Larissa Wehrhahn-Kilian
  • Patent number: 10566426
    Abstract: A body structure and a drift zone are formed in a semiconductor layer, wherein the body structure and the drift zone form a first pn junction. A silicon nitride layer is formed on the semiconductor layer. A silicon oxide layer is formed from at least a vertical section of the silicon nitride layer by oxygen radical oxidation.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: February 18, 2020
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Oliver Hellmund, Peter Irsigler, Jens Peter Konrath, David Laforet, Maik Langner, Markus Neuber, Hans-Joachim Schulze, Ralf Siemieniec, Knut Stahrenberg, Olaf Storbeck
  • Publication number: 20190362976
    Abstract: A method for forming a semiconductor device includes forming a mask layer with a first implantation window on a semiconductor substrate and implanting dopants with a first implantation energy into the semiconductor substrate through the first implantation window to form a first portion of a doping region of the semiconductor device. The mask layer is adapted to form a second implantation window of the mask layer. Further, dopants are implanted with a second implantation energy into the semiconductor substrate through the second implantation window. The second implantation energy differs from the first implantation energy and a lateral dimension of the first implantation window differs from a lateral dimension of the second implantation window.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 28, 2019
    Inventors: Jens Peter Konrath, Jochen Hilsenbeck
  • Publication number: 20190311966
    Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 10, 2019
    Inventors: Jens Peter Konrath, Wolfgang Bergner, Romain Esteve, Richard Gaisberger, Florian Grasse, Jochen Hilsenbeck, Ravi Keshav Joshi, Stefan Kramp, Stefan Krivec, Grzegorz Lupina, Hiroshi Narahashi, Andreas Voerckel, Stefan Woehlert
  • Patent number: 10431681
    Abstract: A semiconductor device includes a gate trench of at least one transistor structure extending into a semiconductor substrate. The gate trench includes at least one sidewall having a bevel portion located adjacent to a bottom of the gate trench. The at least one sidewall of the gate trench is formed by the semiconductor substrate. An angle between the bevel portion and a lateral surface of the semiconductor substrate is between 110? and 160°. A lateral dimension of the bevel portion is larger than 50 nm. Methods for forming the semiconductor device are also provided.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 1, 2019
    Assignee: Infineon Technologies AG
    Inventors: Jens Peter Konrath, Hans-Joachim Schulze
  • Patent number: 10431698
    Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a contact layer in contact with SiC material. The contact layer includes a metal nitride having a nitrogen content in a range of 10 to 50 atomic %. The semiconductor device further includes a non-ohmic contact formed between the SiC material and the contact layer.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: October 1, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Jens Peter Konrath, Ronny Kern, Stefan Krivec, Ulrich Schmid, Laura Stoeber