Patents by Inventor Jeong Don Ihm

Jeong Don Ihm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10770149
    Abstract: A non-volatile memory device includes an output driver to output a data signal. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: September 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-yeon Shin, Jeong-don Ihm, Byung-hoon Jeong, Jung-june Park
  • Publication number: 20200279591
    Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.
    Type: Application
    Filed: May 15, 2020
    Publication date: September 3, 2020
    Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
  • Patent number: 10754563
    Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-joo Jung, Jang-woo Lee, Byung-hoon Jeong, Jeong-don Ihm
  • Publication number: 20200258583
    Abstract: A nonvolatile memory device includes a first memory cell array, a first bi-directional multiplexer, a first register, a second register, a first I/O pad and a second I/O pad. The first memory cell array stores first data. The first bi-directional multiplexer receives the first data and distributes the first data into first sub-data and second sub-data. The first register stores first sub-data from the first bi-directional multiplexer. The second register stores second sub-data from a second bi-directional multiplexer. The first I/O pad outputs the first sub-data from the first register to outside. The second I/O pad outputs the second sub-data from the second register to the outside.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 13, 2020
    Inventors: SEUNG WOO YU, SANG LOK KIM, BYUNG KWAN CHUN, BYUNG HOON JEONG, JEONG DON IHM, YOUNG DON CHOI
  • Publication number: 20200258589
    Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
  • Patent number: 10741225
    Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Su Jang, Man-Jae Yang, Jeong-Don Ihm, Go-Eun Jung, Byung-Hoon Jeong, Young-Don Choi
  • Publication number: 20200227131
    Abstract: Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.
    Type: Application
    Filed: August 12, 2019
    Publication date: July 16, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae Hoon NA, Jang Woo LEE, Jin Do BYUN, Jeong Don IHM
  • Publication number: 20200194040
    Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Inventors: DONG-SU JANG, MAN-JAE YANG, JEONG-DON IHM, GO-EUN JUNG, BYUNG-HOON JEONG, YOUNG-DON CHOI
  • Patent number: 10679717
    Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: June 9, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 10672436
    Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: June 2, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 10666249
    Abstract: A semiconductor package including a first master-slave status circuit configured to store one of a first signal or a second signal independently from a second master-slave status circuit, store the first signal in response to receiving a first initial signal from a first initialization circuit, the second master-slave status circuit configured to store one of the first signal or the second signal, store the first signal in response to receiving a second initial signal from a second initialization circuit, the first initialization circuit configured to provide the first initial signal to the first master-slave status circuit, the second initialization circuit configured to provide the second initial signal to the second master-slave status circuit, and a first master-slave determination circuit connected to the second master-slave status circuit, the first master-slave determination circuit configured to provide the second signal to the second master-slave status circuit may be provided.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 26, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae Hoon Na, Seon Kyoo Lee, Jeong Don Ihm, Byung Hoon Jeong, Young Don Choi
  • Patent number: 10600454
    Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-su Jang, Man-jae Yang, Jeong-don Ihm, Go-eun Jung, Byung-hoon Jeong, Young-don Choi
  • Publication number: 20200091021
    Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.
    Type: Application
    Filed: March 19, 2019
    Publication date: March 19, 2020
    Inventors: Min-Jae Lee, Sang-Lok Kim, Byung-Hoon Jeong, Tae-Sung Lee, Jeong-Don Ihm, Jae-Yong Jeong, Young-Don Choi
  • Publication number: 20200066317
    Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-june Park, Jeong-don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
  • Patent number: 10559373
    Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Publication number: 20200014383
    Abstract: A semiconductor package including a first master-slave status circuit configured to store one of a first signal or a second signal independently from a second master-slave status circuit, store the first signal in response to receiving a first initial signal from a first initialization circuit, the second master-slave status circuit configured to store one of the first signal or the second signal, store the first signal in response to receiving a second initial signal from a second initialization circuit, the first initialization circuit configured to provide the first initial signal to the first master-slave status circuit, the second initialization circuit configured to provide the second initial signal to the second master-slave status circuit, and a first master-slave determination circuit connected to the second master-slave status circuit, the first master-slave determination circuit configured to provide the second signal to the second master-slave status circuit may be provided.
    Type: Application
    Filed: November 30, 2018
    Publication date: January 9, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae Hoon NA, Seon Kyoo LEE, Jeong Don IHM, Byung Hoon JEONG, Young Don CHOI
  • Patent number: 10497412
    Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: December 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seon-Kyoo Lee, Jeong-Don Ihm, Byung-Hoon Jeong, Dae-Woon Kang
  • Patent number: 10482935
    Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: November 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-june Park, Jeong-Don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
  • Patent number: 10482937
    Abstract: A memory device that includes an interface that receives a data signal and a strobe signal from an external device, the strobe signal corresponding to the data signal; a strobe buffer that receives the strobe signal from the interface; a phase detection unit that detects a phase difference between the data signal output from the interface and the strobe signal output from the strobe buffer; a phase adjust unit that adjusts a phase of the strobe signal output from the strobe buffer based on the phase difference; and a sampling unit that samples the data signal output from the interface based on the strobe signal output from the phase adjust unit.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: November 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang Woo Lee, Jeong Don Ihm, Byung Hoon Jeong
  • Publication number: 20190325979
    Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI