Patents by Inventor Jeong Don Ihm

Jeong Don Ihm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10439632
    Abstract: A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: October 8, 2019
    Assignee: SAMSING ELECTRONICS CO., LTD.
    Inventors: Anil Kavala, Seon-kyoo Lee, Byung-hoon Jeong, Jeong-don Ihm, Young-don Choi
  • Patent number: 10438635
    Abstract: An apparatus includes data transmitter having first through N-th data drivers configured to provide first through N-th data signals, respectively, and a strobe driver configured to provide a strobe signal, and a data receiver having a strobe buffer configured to generate a control signal based on the strobe signal, and first through N-th sense amplifiers configured to sense N-bit data based on the control signal, a reference signal and the first through N-th data signals. The bus includes a strobe TSV configured to connect the strobe driver with the strobe buffer, and first through N-th data TSVs configured to connect the first through N-th data drivers with the first through N-th sense amplifiers, respectively. A reference signal supplier controls the reference signal such that a discharge speed of the reference signal is slower than a discharge speed of each of the first through N-th data signals during data transmission.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: October 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seon-Kyoo Lee, Dae-Hoon Na, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Publication number: 20190279733
    Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
    Type: Application
    Filed: May 30, 2019
    Publication date: September 12, 2019
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Publication number: 20190214064
    Abstract: A memory device that includes an interface that receives a data signal and a strobe signal from an external device, the strobe signal corresponding to the data signal; a strobe buffer that receives the strobe signal from the interface; a phase detection unit that detects a phase difference between the data signal output from the interface and the strobe signal output from the strobe buffer; a phase adjust unit that adjusts a phase of the strobe signal output from the strobe buffer based on the phase difference; and a sampling unit that samples the data signal output from the interface based on the strobe signal output from the phase adjust unit.
    Type: Application
    Filed: July 12, 2018
    Publication date: July 11, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jang Woo LEE, Jeong Don IHM, Byung Hoon JEONG
  • Patent number: 10340022
    Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Publication number: 20190198067
    Abstract: An apparatus includes data transmitter having first through N-th data drivers configured to provide first through N-th data signals, respectively, and a strobe driver configured to provide a strobe signal, and a data receiver having a strobe buffer configured to generate a control signal based on the strobe signal, and first through N-th sense amplifiers configured to sense N-bit data based on the control signal, a reference signal and the first through N-th data signals. The bus includes a strobe TSV configured to connect the strobe driver with the strobe buffer, and first through N-th data TSVs configured to connect the first through N-th data drivers with the first through N-th sense amplifiers, respectively. A reference signal supplier controls the reference signal such that a discharge speed of the reference signal is slower than a discharge speed of each of the first through N-th data signals during data transmission.
    Type: Application
    Filed: August 27, 2018
    Publication date: June 27, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seon-Kyoo LEE, Dae-Hoon NA, Jeong-Don IHM, Byung-Hoon JEONG, Young-Don CHOI
  • Publication number: 20190158109
    Abstract: A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 23, 2019
    Inventors: Anil KAVALA, Seon-kyoo LEE, Byung-hoon JEONG, Jeong-don IHM, Young-don CHOI
  • Patent number: 10291275
    Abstract: A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: May 14, 2019
    Assignee: Samsung Electronics Co., LTD.
    Inventors: Seon-Kyoo Lee, Byung-Hoon Jeong, Jeong-Don Ihm, Young-Don Choi
  • Publication number: 20190139613
    Abstract: A non-volatile memory device includes an output driver to output a data signal. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.
    Type: Application
    Filed: July 30, 2018
    Publication date: May 9, 2019
    Inventors: Ji-yeon SHIN, Jeong-don IHM, Byung-hoon JEONG, Jung-june PARK
  • Publication number: 20190139585
    Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.
    Type: Application
    Filed: August 8, 2018
    Publication date: May 9, 2019
    Inventors: EUN-JI KIM, JUNG-JUNE PARK, JEONG-DON IHM, BYUNG-HOON JEONG, YOUNG-DON CHOI
  • Publication number: 20190096447
    Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.
    Type: Application
    Filed: May 9, 2018
    Publication date: March 28, 2019
    Inventors: DONG-SU JANG, Man-jae YANG, Jeong-don IHM, Go-eun JUNG, Byung-hoon JEONG, Young-don CHOI
  • Publication number: 20190079699
    Abstract: A memory system and a buffer device include a structure for performing training operations for a plurality of memory devices to ensure data reliability. A memory controller is configured to control a memory operation for a plurality of memory devices. A memory module includes the plurality of memory devices and a buffer device connected between the memory devices and the memory controller. Training operations for the memory devices to be performed by the buffer device including a training block with a signal delay circuit, and the memory controller performs the training operations by controlling the training block.
    Type: Application
    Filed: May 15, 2018
    Publication date: March 14, 2019
    Inventors: Jang-woo LEE, Jeong-don IHM, Byung-hoon JEONG
  • Publication number: 20190050159
    Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.
    Type: Application
    Filed: February 27, 2018
    Publication date: February 14, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Won-joo Jung, Jang-woo Lee, Byung-hoon Jeong, Jeong-don Ihm
  • Patent number: 10205431
    Abstract: A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: February 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Woon Kang, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 10176878
    Abstract: A single-ended sense amplifier and a memory device including the same are presented. A sense amplifier, which senses and amplifies data of a memory cell, may include a precharge circuit pre-charging a data line which is connected to the memory cell and provides a sensing voltage, and a reference line which provides a reference voltage, with a power supply voltage; a reference voltage generating circuit which generates the reference voltage by discharging the reference line based on a reference current, and adjusts an amount of the reference current based on the data of the memory cell; and a comparator which compares the sensing voltage and the reference voltage, and outputs a comparison result as the data of the memory cell.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: January 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-don Ihm, Siddharth Katare, Hyun-jin Kim
  • Patent number: 10171269
    Abstract: An equalizer circuit may include an equalizer controller and a plurality of equalizers. The equalizer controller may prove separate sets of enable signals, delay control signals and voltage control signals to the separate equalizers based on a control signal. The equalizers provide equalizer signals to separate connection nodes between separate pairs of logic circuits. An equalizer may be selectively activated based on a received enable signal. An equalizer may include a delay control circuit and a voltage control circuit. The delay control circuit may delay a received transfer signal to generate a delayed transfer signal based on a received delay control signal. The voltage control circuit may generate an equalizer signal based on the delayed transfer signal and a received voltage control signal. The equalizer circuit may reduce inter-symbol interference in the integrated circuit based on providing the equalizer signals to the connection nodes between the logic circuits.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: January 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seon-Kyoo Lee, Jeong-Don Ihm, Anil Kavala, Byung-Hoon Jeong
  • Publication number: 20180350414
    Abstract: Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.
    Type: Application
    Filed: May 17, 2018
    Publication date: December 6, 2018
    Applicant: Samsung Electronics Co, Ltd
    Inventors: Jung-june PARK, Jeong-Don Ihm, Byung-hoon Jeong, Eun-ji Kim, Ji-yeon Shin, Young-don Choi
  • Publication number: 20180336958
    Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
    Type: Application
    Filed: May 11, 2018
    Publication date: November 22, 2018
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 10132865
    Abstract: A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: November 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seon-kyoo Lee, Jeong-don Ihm, Byung-hoon Jeong, Dae-woon Kang, Tae-sung Lee, Sang-lok Kim
  • Publication number: 20180315461
    Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.
    Type: Application
    Filed: July 3, 2018
    Publication date: November 1, 2018
    Inventors: Seon-Kyoo LEE, Jeong-Don IHM, Byung-Hoon JEONG, Dae-Woon KANG