Patents by Inventor Jeong-gil Lee

Jeong-gil Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7998810
    Abstract: A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: August 16, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-hee Kim, Gil-heyun Choi, Sang-woo Lee, Chang-won Lee, Jin-ho Park, Eun-ji Jung, Jeong-gil Lee
  • Publication number: 20110189846
    Abstract: A method of manufacturing a non-volatile memory device including a tunnel oxide layer, a preliminary charge storing layer and a dielectric layer on a semiconductor layer is disclosed. A first polysilicon layer is formed on the dielectric layer. A barrier layer and a second polysilicon layer are formed on the first polysilicon layer. The second polysilicon layer, the barrier layer, the first polysilicon layer, the dielectric layer, the preliminary charge storing layer and the tunnel oxide layer are patterned to form a tunnel layer pattern, a charge storing layer pattern, a dielectric layer pattern, a first control gate pattern, a barrier layer pattern and a second polysilicon pattern. A nickel layer is formed on the second polysilicon layer. Heat treatment is performed with respect to the second polysilicon pattern and the nickel layer to form a second control gate pattern including NiSi on the barrier layer pattern.
    Type: Application
    Filed: February 4, 2011
    Publication date: August 4, 2011
    Inventors: Jeong Gil Lee, Chang-Won Lee, Sang-Woo Lee, Sun-Woo Lee, Ki-Hyun Hwang, Jae-Hwa Park, Eun-Ji Jung
  • Patent number: 7968410
    Abstract: A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: June 28, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-ji Jung, Sang-woo Lee, Jeong-gil Lee, Gil-heyun Choi, Chang-won Lee, Byung-hee Kim, Jin-ho Park
  • Patent number: 7897500
    Abstract: A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: March 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-ji Jung, Dae-yong Kim, Gil-heyun Choi, Byung-hee Kim, Woong-hee Sohn, Hyun-su Kim, Jang-hee Lee, Eun-ok Lee, Jeong-gil Lee
  • Publication number: 20100112772
    Abstract: A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.
    Type: Application
    Filed: July 27, 2009
    Publication date: May 6, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Eun-ji Jung, Sang-woo Lee, Jeong-gil Lee, Gil-heyun Choi, Chang-won Lee, Byung-hee Kim, Jin-ho Park
  • Publication number: 20100105198
    Abstract: A method of forming a gate electrode of a semiconductor device includes forming a first polysilicon layer in a peripheral circuit region of a substrate, forming a barrier layer on the first polysilicon layer, the barrier layer providing an ohmic contact, forming a stack structure including a tunneling insulation layer, an electric charge storing layer, and a blocking insulation layer in a memory cell region of the substrate, forming a second polysilicon layer on the barrier layer and the blocking insulation layer, and siliciding the second polysilicon layer and forming a silicide gate electrode.
    Type: Application
    Filed: July 22, 2009
    Publication date: April 29, 2010
    Inventors: Sang-woo Lee, Gil-heyun Choi, Chang-won Lee, Byung-hee Kim, Jin-ho Park, Eun-ji Jung, Jeong-gil Lee
  • Publication number: 20090325371
    Abstract: A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.
    Type: Application
    Filed: April 16, 2009
    Publication date: December 31, 2009
    Inventors: Byung-hee Kim, Gil-heyun Choi, Sang-woo Lee, Chang-won Lee, Jin-ho Park, Eun-ji Jung, Jeong-gil Lee
  • Publication number: 20090191699
    Abstract: A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers.
    Type: Application
    Filed: November 24, 2008
    Publication date: July 30, 2009
    Inventors: Eun-ji Jung, Dae-yong Kim, Gil-heyun Choi, Byung-hee Kim, Woong-hee Sohn, Hyun-su Kim, Jang-hee Lee, Eun-ok Lee, Jeong-gil Lee
  • Publication number: 20090154442
    Abstract: A method and an apparatus for reducing Digital-to-Analog Conversion (DAC) bits at a transmitter of a Frequency Division Multiple Access (FDMA) system reduces a number of the bits for conversion so as to save power and reduce the cost of operation. The method can include generating a digital signal gain control value and an analog signal gain control value using subcarrier allocation information, a required Signal to Noise Ratio (SNR), and a Peak to Average Power Ratio (PAPR); controlling a gain of a signal input to a digital-to-analog converter using the digital signal gain control value; converting a digital signal of the controlled gain to an analog signal using the digital-to-analog converter; and restoring an original signal by controlling a gain of a signal output from the digital-to-analog converter using the analog signal gain control value.
    Type: Application
    Filed: December 18, 2008
    Publication date: June 18, 2009
    Inventors: Jun-Kyu KANG, In-Tae Kang, Jeong-Gil Lee, Bo-Rham Lee, Sang-Min Bae
  • Patent number: 5399518
    Abstract: A method for manufacturing a double-cylindrical storage electrode of a capacitor of a semiconductor memory device, utilizes an outer etching mask for forming an outer cylinder and an inner etching mask for forming an inner cylinder. After forming a conductive structure on a semiconductor substrate, an outer etching mask for forming an outer cylinder and an inner etching mask for forming an inner cylinder are formed on the conductive structure. Then, the conductive structure is anisotropically etched using the outer and inner etching masks, thereby forming a double-cylindrical first electrode. Since a double-cylindrical storage electrode can be obtained from a single conductive layer, the influence of native oxidation circumvented. In addition, the double-cylindrical storage electrode of the capacitor according to the present invention decreases the risk of structural fragmenting because the electrode is obtained from one material layer, instead of a combination of layers as is conventionally-known.
    Type: Grant
    Filed: July 15, 1993
    Date of Patent: March 21, 1995
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-pil Sim, Joo-young Yun, Chang-kyu Hwang, Jeong-gil Lee, Chul-ho Shin, Won-woo Lee