Patents by Inventor Jeong-lim Nam
Jeong-lim Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9818972Abstract: An organic light-emitting device with a sealing layer covering a light-emitting diode, wherein the sealing layer comprises n number of sealing units, each comprising a sequential stack of an organic film and an inorganic film, wherein n is an integer of 1 or greater and a method of manufacturing the same.Type: GrantFiled: September 9, 2013Date of Patent: November 14, 2017Assignee: Samsung Display Co., Ltd.Inventors: Sang-Jun Choi, Won-Duk Jung, Jeong-Lim Nam
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Patent number: 9099662Abstract: In an aspect, a substrate for a display device that includes a plastic substrate and a planarization layer is provided.Type: GrantFiled: March 14, 2013Date of Patent: August 4, 2015Assignee: Samsung Display Co., Ltd.Inventors: Sang-Jun Choi, Won-Duk Jung, Jeong-Lim Nam
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Publication number: 20140140015Abstract: In an aspect, a substrate for a display device that includes a plastic substrate and a planarization layer is provided.Type: ApplicationFiled: March 14, 2013Publication date: May 22, 2014Applicant: SAMSUNG DISPLAY CO., LTD.Inventors: Sang-Jun Choi, Won-Duk Jung, Jeong-Lim Nam
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Publication number: 20140070195Abstract: An organic light-emitting device with a sealing layer covering a light-emitting diode, wherein the sealing layer comprises n number of sealing units, each comprising a sequential stack of an organic film and an inorganic film, wherein n is an integer of 1 or greater and a method of manufacturing the same.Type: ApplicationFiled: September 9, 2013Publication date: March 13, 2014Applicant: Samsung Display Co., Ltd.Inventors: Sang-Jun Choi, Won-Duk Jung, Jeong-Lim Nam
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Patent number: 8278221Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.Type: GrantFiled: July 13, 2011Date of Patent: October 2, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-won Koh, Han-ku Cho, Jeong-lim Nam, Gi-sung Yeo, Joon-soo Park, Ji-young Lee
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Publication number: 20110269294Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.Type: ApplicationFiled: July 13, 2011Publication date: November 3, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cha-won Koh, Han-ku Cho, Jeong-lim Nam, Gi-sung Yeo, Joon-soo Park, Ji-young Lee
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Patent number: 8003543Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.Type: GrantFiled: April 14, 2010Date of Patent: August 23, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-won Koh, Han-ku Cho, Jeong-lim Nam, Gi-sung Yeo, Joon-soo Park, Ji-young Lee
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Patent number: 7829437Abstract: In a method of manufacturing a semiconductor device, a first substrate and a second substrate, which include a plurality of memory cells and selection transistors, respectively, are provided. A first insulating interlayer and a second insulating interlayer are formed on the first substrate and the second substrate, respectively, to cover the memory cells and the selection transistors. A lower surface of the second substrate is partially removed to reduce a thickness of the second substrate. The lower surface of the second substrate is attached to the first insulating interlayer. Plugs are formed through the second insulating interlayer, the second substrate and the first insulating interlayer to electrically connect the selection transistors in the first substrate and the second substrate to the plugs. Thus, impurity ions in the first substrate will not diffuse during a thermal treatment process.Type: GrantFiled: June 16, 2008Date of Patent: November 9, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hoo Kim, Hyun Park, Byung-Hong Chung, Jeong-Lim Nam
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Publication number: 20100197139Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.Type: ApplicationFiled: April 14, 2010Publication date: August 5, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cha-won Koh, Han-ku Cho, Jeong-lim Nam, Gi-sung Yeo, Joon-soo Park, Ji-young Lee
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Patent number: 7732341Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.Type: GrantFiled: March 23, 2007Date of Patent: June 8, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-won Koh, Han-ku Cho, Jeong-lim Nam, Gi-sung Yeo, Joon-soo Park, Ji-young Lee
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Patent number: 7687369Abstract: A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardmask patterns in the first spaces by a damascene process, removing the mold patterns, etching the insulating film through the metal hardmask patterns to form insulating film patterns with second spaces therebetween, the second spaces having the first layout, and forming metal interconnect patterns having the first layout in the second spaces by the damascene process.Type: GrantFiled: September 4, 2007Date of Patent: March 30, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-won Koh, Jeong-lim Nam, Gi-sung Yeo, Sang-jin Kim, Sung-gon Jung
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Patent number: 7678650Abstract: Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.Type: GrantFiled: May 20, 2009Date of Patent: March 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-Won Koh, Byung-Hong Chung, Sang-Gyun Woo, Jeong-Lim Nam, Seok-Hwan Oh, Jai-Hyuk Song, Hyun Park, Yool Kang
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Patent number: 7645668Abstract: A memory device includes a charge trapping layer on a substrate, an insulating layer on the substrate adjacent to the charge trapping layer and exposing an upper surface of the charge trapping layer, a dielectric layer on the exposed charge trapping layer and on the insulating layer, and an electrode on the dielectric layer, the electrode corresponding to the charge trapping layer.Type: GrantFiled: November 9, 2006Date of Patent: January 12, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Seob Kim, Jeong-Lim Nam, Won-Jin Kim, Guk-Hyon Yon
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Publication number: 20090258473Abstract: Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.Type: ApplicationFiled: May 20, 2009Publication date: October 15, 2009Inventors: Cha-Won Koh, Byung-Hong Chung, Sang-Gyun Woo, Jeong-Lim Nam, Seok-Hwan Oh, Jai-Hyuk Song, Hyun Park, Yool Kang
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Patent number: 7560768Abstract: Provided are a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.Type: GrantFiled: November 9, 2006Date of Patent: July 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-Won Koh, Byung-Hong Chung, Sang-Gyun Woo, Jeong-Lim Nam, Seok-Hwan Oh, Jai-Hyuk Song, Hyun Park, Yool Kang
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Patent number: 7540970Abstract: Methods of fabricating a semiconductor device are provided. Methods of forming a finer pattern of a semiconductor device using a buffer layer for retarding, or preventing, bridge formation between patterns in the formation of a finer pattern below resolution limits of a photolithography process by double patterning are also provided. A first hard mask layer and/or a second hard mask layer may be formed on a layer of a substrate to be etched. A first etch mask pattern of a first pitch may be formed on the second hard mask layer. After a buffer layer is formed on the overall surface of the substrate, a second etch mask pattern of a second pitch may be formed thereon in a region between the first etch mask pattern. The buffer layer may be anisotropically etched using the second etch mask pattern as an etch mask, forming a buffer layer pattern.Type: GrantFiled: May 8, 2006Date of Patent: June 2, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-Won Koh, Sang-Gyun Woo, Jeong-Lim Nam, Kyeong-Koo Chi, Seok-Hwan Oh, Gi-Sung Yeo, Seung-Pil Chung, Heung-Sik Park
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Publication number: 20090004826Abstract: In a method of manufacturing a semiconductor device, a first substrate and a second substrate, which include a plurality of memory cells and selection transistors, respectively, are provided. A first insulating interlayer and a second insulating interlayer are formed on the first substrate and the second substrate, respectively, to cover the memory cells and the selection transistors. A lower surface of the second substrate is partially removed to reduce a thickness of the second substrate. The lower surface of the second substrate is attached to the first insulating interlayer. Plugs are formed through the second insulating interlayer, the second substrate and the first insulating interlayer to electrically connect the selection transistors in the first substrate and the second substrate to the plugs. Thus, impurity ions in the first substrate will not diffuse during a thermal treatment process.Type: ApplicationFiled: June 16, 2008Publication date: January 1, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Hoo Kim, Hyun Park, Byung-Hong Chung, Jeong-Lim Nam
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Publication number: 20080200026Abstract: A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardmask patterns in the first spaces by a damascene process, removing the mold patterns, etching the insulating film through the metal hardmask patterns to form insulating film patterns with second spaces therebetween, the second spaces having the first layout, and forming metal interconnect patterns having the first layout in the second spaces by the damascene process.Type: ApplicationFiled: September 4, 2007Publication date: August 21, 2008Inventors: Cha-won Koh, Jeong-lim Nam, Gi-sung Yeo, Sang-jin Kim, Sung-gon Jung
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Publication number: 20080090419Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.Type: ApplicationFiled: March 23, 2007Publication date: April 17, 2008Inventors: Cha-won Koh, Han-ku Cho, Jeong-lim Nam, Gi-sung Yeo, Joon-soo Park, Ji-young Lee
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Publication number: 20080067571Abstract: A memory device includes a charge trapping layer on a substrate, an insulating layer on the substrate adjacent to the charge trapping layer and exposing an upper surface of the charge trapping layer, a dielectric layer on the exposed charge trapping layer and on the insulating layer, and an electrode on the dielectric layer, the electrode corresponding to the charge trapping layer.Type: ApplicationFiled: November 9, 2006Publication date: March 20, 2008Inventors: Chang-Seob Kim, Jeong-Lim Nam, Won-Jin Kim, Guk-Hyon Yon