Patents by Inventor Jeong-Nam Han

Jeong-Nam Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150279991
    Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.
    Type: Application
    Filed: May 26, 2015
    Publication date: October 1, 2015
    Inventors: Sang-Jine PARK, Bo-Un YOON, Jeong-Nam HAN, Myung-Geun SONG
  • Patent number: 9136135
    Abstract: A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, and etching sides of the gate pattern using a first wet-etching process to form a first recess. The first wet-etching process includes using an etchant containing a first chemical substance including a hydroxyl functional group (—OH) and a second chemical substance capable of oxidizing the substrate. The concentration of the second chemical substance is 1.5 times or less the concentration of the first chemical substance.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Jik Baek, Ji-Hoon Cha, Bo-Un Yoon, Kwang-Wook Lee, Jeong-Nam Han
  • Publication number: 20150187946
    Abstract: A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.
    Type: Application
    Filed: August 8, 2014
    Publication date: July 2, 2015
    Inventors: Sang-Jine PARK, Bo-Un YOON, Ha-Young JEON, Byung-Kwon CHO, Jeong-Nam HAN
  • Publication number: 20150162221
    Abstract: Provided are an apparatus and method for treating wafers using a supercritical fluid. The wafer treatment apparatus includes a plurality of chambers; a first supply supplying a first fluid in a supercritical state; a second supply supplying a mixture of the first fluid and a second fluid; a plurality of first and second valves; and a controller selecting a first chamber of the plurality of chambers for wafer treatment to control the open/closed state of each of the plurality of first valves so that the first fluid can be supplied only to the first chamber of the plurality of chambers and selecting a second chamber of the plurality of chambers to control the open/closed state of each of the plurality of second valves so that the mixture of the first fluid and a second fluid can be supplied only to the second chamber of the plurality of chambers.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 11, 2015
    Inventors: Hyo-San Lee, Chang-ki Hong, Kun-tack Lee, Jeong-nam Han
  • Patent number: 9054210
    Abstract: A method of fabricating a semiconductor device, the method including forming on a substrate a transistor that includes a gate electrode and a source and drain region, forming an interlayer insulating film on the transistor, forming a contact hole in the interlayer insulating film to expose a top surface of the source and drain region, and a thin film is formed at an interface between the contact hole and the exposed top surface of the source and drain region. The method further including selectively removing at least a portion of the thin film by performing an etching process in a non-plasma atmosphere, forming an ohmic contact film on the source and drain region where at least a portion of the thin film was selectively removed, and forming a contact plug by filling the contact hole with a conductive material.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: June 9, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Jine Park, Doo-Sung Yun, Bo-Un Yoon, Jeong-Nam Han, Kee-Sang Kwon, Won-Sang Choi
  • Patent number: 9040415
    Abstract: A method for forming a trench includes etching an oxide layer to form a trench therein, conformally forming a first reaction layer along a surface of the trench, the first reaction layer including a first region on an upper portion of the trench and a second region on a lower portion of the trench, forming a barrier layer by reacting a first amount of etching gas with the first region of the first reaction layer, and etching the oxide layer on a lower portion of the second region by reacting a second amount of etching gas with the second region of the first reaction layer, the second amount of etching gas being greater than the first amount of etching gas.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: May 26, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Young-Sang Youn, Jeong-Nam Han, Kee-Sang Kwon, Doo-Sung Yun, Byung-Kwon Cho, Ji-Hoon Cha
  • Publication number: 20150050793
    Abstract: A method for forming a trench includes etching an oxide layer to form a trench therein, conformally forming a first reaction layer along a surface of the trench, the first reaction layer including a first region on an upper portion of the trench and a second region on a lower portion of the trench, forming a barrier layer by reacting a first amount of etching gas with the first region of the first reaction layer, and etching the oxide layer on a lower portion of the second region by reacting a second amount of etching gas with the second region of the first reaction layer, the second amount of etching gas being greater than the first amount of etching gas.
    Type: Application
    Filed: May 23, 2014
    Publication date: February 19, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Jine PARK, Bo-Un YOON, Young-Sang YOUN, Jeong-Nam HAN, Kee-Sang KWON, Doo-Sung YUN, Byung-Kwon CHO, Ji-Hoon CHA
  • Patent number: 8951383
    Abstract: Provided are an apparatus and method for treating wafers using a supercritical fluid. The wafer treatment apparatus includes a plurality of chambers; a first supply supplying a first fluid in a supercritical state; a second supply supplying a mixture of the first fluid and a second fluid; a plurality of first and second valves; and a controller selecting a first chamber of the plurality of chambers for wafer treatment to control the open/closed state of each of the plurality of first valves so that the first fluid can be supplied only to the first chamber of the plurality of chambers and selecting a second chamber of the plurality of chambers to control the open/closed state of each of the plurality of second valves so that the mixture of the first fluid and a second fluid can be supplied only to the second chamber of the plurality of chambers.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-san Lee, Chang-ki Hong, Kun-tack Lee, Jeong-nam Han
  • Publication number: 20140322881
    Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.
    Type: Application
    Filed: July 9, 2014
    Publication date: October 30, 2014
    Inventors: Sang-Jine Park, Bo-Un Yoon, Jeong-Nam Han, Myung-Geun Song
  • Publication number: 20140231010
    Abstract: A chemical supplier includes a chemical reservoir containing a chemical mixture at a room temperature, an inner space of the chemical reservoir being separated from surroundings, a supply line through which the chemical mixture is supplied to a process chamber from the chemical reservoir, an inline heater positioned on the supply line and heating the chemical mixture in the supply line to a process temperature, and a power source driving the chemical mixture to move the chemical mixture toward the process chamber.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 21, 2014
    Inventors: Sang-Jine PARK, Bo-Un YOON, Jeong-Nam HAN, Kee-Sang KWON, Doo-Sung YUN, Won-Sang CHOI
  • Publication number: 20140227857
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Application
    Filed: February 7, 2014
    Publication date: August 14, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: YOUNG-SANG YOUN, MYUNG-GEUN SONG, JI-HOON CHA, JAE-JIK BAEK, BO-UN YOON, JEONG-NAM HAN
  • Patent number: 8803248
    Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 12, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Jeong-Nam Han, Myung-Geun Song
  • Patent number: 8796107
    Abstract: Provided are methods for fabricating a semiconductor device. The methods include forming a hard mask pattern on a semiconductor substrate, forming a first trench having a first width and a second trench having a second width on the semiconductor substrate using the hard mask pattern as a mask, forming an oxide film on the hard mask pattern and the first and second trenches, forming first and second isolation films on the first and second trenches by planarizing the oxide film until the hard mask pattern is exposed, and etching the first isolation film by a first thickness by performing dry cleaning on the semiconductor substrate and etching the second isolation film by a second thickness different from the first thickness.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: August 5, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kevin Ahn, Bo-Un Yoon, Jeong-Nam Han
  • Patent number: 8790470
    Abstract: Provided herein are etching, cleaning and drying methods using a supercritical fluid, and a chamber system for conducting the same. The etching method includes etching the material layer using a supercritical carbon dioxide in which an etching chemical is dissolved, and removing an etching by-product created from a reaction between the material layer and the etching chemical using a supercritical carbon dioxide in which a cleaning chemical is dissolved. Methods of manufacturing a semiconductor device are also provided.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-san Lee, Chang-Ki Hong, Kun-Tack Lee, Woo-Gwan Shim, Jeong-Nam Han, Jung-Min Oh, Kwon-Taek Lim, Ha-Soo Hwang, Haldorai Yuvaraj, Jae-Mok Jung
  • Publication number: 20140206169
    Abstract: A method of forming a semiconductor device can include providing a plasma nitrided exposed top surface including an active region and an isolation region. The exposed top surface including the active region and the isolation region can be subjected to etching to form a deeper recess in the active region that in the isolation region and an unmerged epitaxial stress film can be grown in the deeper recess.
    Type: Application
    Filed: March 15, 2013
    Publication date: July 24, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ji Hoon Cha, Jae-Jik Baek, Bo-Un Yoon, Young-Sang Youn, Jeong-Nam Han
  • Patent number: 8709942
    Abstract: In a method for fabricating a semiconductor device, a substrate is provided including an interlayer dielectric layer and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric layer through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric layer and the second hard mask pattern to fill the first trench. An upper portion of the second hard mask pattern is exposed by partially removing the filler material. The second hard mask pattern is removed, and remaining filler material is removed from the first trench. A wiring is formed by filling the first trench with a conductive material.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Doo-Sung Yun, Bo-Un Yoon, Il-Young Yoon, Jeong-Nam Han
  • Patent number: 8685272
    Abstract: A composition for etching a silicon oxide layer, a method of etching a semiconductor device, and a composition for etching a semiconductor device including a silicon oxide layer and a nitride layer including hydrogen fluoride, an anionic polymer, and deionized water, wherein the anionic polymer is included in an amount of about 0.001 to about 2 wt % based on the total weight of the composition for etching a silicon oxide layer, and an etch selectivity of the silicon oxide layer with respect to a nitride layer is about 80 or greater.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Go-Un Kim, Hyo-San Lee, Myung-Kook Park, Ho-Seok Yang, Jeong-Nam Han, Chang-Ki Hong
  • Publication number: 20140080296
    Abstract: A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, and etching sides of the gate pattern using a first wet-etching process to form a first recess. The first wet-etching process includes using an etchant containing a first chemical substance including a hydroxyl functional group (—OH) and a second chemical substance capable of oxidizing the substrate. The concentration of the second chemical substance is 1.5 times or less the concentration of the first chemical substance.
    Type: Application
    Filed: July 17, 2013
    Publication date: March 20, 2014
    Inventors: Jae-Jik BAEK, Ji-Hoon CHA, Bo-Un YOON, Kwang-Wook LEE, Jeong-Nam HAN
  • Patent number: 8673724
    Abstract: Provided are methods of fabricating a semiconductor device that include providing a substrate that includes a first region having a gate pattern and a second region having a first trench and an insulating layer that fills the first trench. A portion of a sidewall of the first trench is exposed by etching part of the insulating layer and a first spacer is formed on a sidewall of the gate pattern. A second spacer is formed on the exposed sidewall of the first trench, wherein the first spacer and the second spacer are formed simultaneously.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Doo-Sung Yun, Bo-Un Yoon, Jeong-Nam Han
  • Patent number: 8652915
    Abstract: A method of fabricating a semiconductor device can be provided by etching sidewalls of a preliminary trench in a substrate that are between immediately adjacent gate electrode structures, to recess the sidewalls further beneath the gate electrode structures to provide recessed sidewalls. Then, the recessed sidewalls and a bottom of the preliminary trench can be etched using crystallographic anisotropic etching to form a hexagonally shaped trench in the substrate.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kevin Ahn, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Jeong-Nam Han