Patents by Inventor Jeong-Uk Han

Jeong-Uk Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10571176
    Abstract: Disclosed herein are an air conditioner and a method for controlling the same. The air conditioner includes an indoor temperature measuring unit that measures an indoor air temperature, an outdoor temperature measuring unit that measures an outdoor air temperature, a heat exchanger temperature measuring unit that measures an inlet temperature of one or more indoor heat exchangers and an outlet temperature thereof, and a processor that determines a reference superheat degree using the indoor air temperature and the outdoor air temperature, obtains a difference between the inlet temperature and the outlet temperature of the one or more indoor heat exchangers, compares the difference between the inlet temperature and the outlet temperature of the one or more indoor heat exchangers and the reference superheat degree, and determines whether a circulation amount of a refrigerant is normal according to a result of the comparison.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: February 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Sik Han, Jeong Uk Park, Jong Woon Kim, Tae Woo Kim, Hyun Jin Bae
  • Patent number: 10466527
    Abstract: A display device is provided. The display device includes a first base substrate, a gate line on the first base substrate and extending in a first direction, a data line disposed on the first base substrate, insulated from the gate line, and extending in a second direction, which crosses the first direction, a switch on the first base substrate and electrically connected to the gate line and the data line, an insulating layer on the switch, a first electrode on the insulating layer, a light-shielding conductive layer directly contacting the first electrode and overlapping the switch, and a second electrode insulated from the first electrode and the light-shielding conductive layer, at least partially overlapping the first electrode, and electrically connected to the switch.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dong Ju Yang, Seul Ki Kim, Hyun Jung Lee, Hyo Jin Kim, Kap Soo Yoon, Jeong Hyun Lee, Yun Seok Han, Jeong Uk Heo
  • Publication number: 20190177898
    Abstract: Disclosed are a lifter having an improved structure to improve washing performance and a washing machine having the lifter. The washing machine includes a drum and a lifter coupled to the inside of the drum, wherein the lifter is provided in the form of a closed curve in which a space is formed at a central portion thereof.
    Type: Application
    Filed: July 4, 2017
    Publication date: June 13, 2019
    Inventors: Jung Hee LEE, Jeong Hoon KANG, Kwan Woo HONG, Dae Uk KANG, Min Sung KIM, Ju Bum HAN
  • Patent number: 10295869
    Abstract: A display device is provided. The display device includes: a first substrate that comprises a first base substrate, an insulating layer located on the first base substrate, and a barrier layer located on the insulating layer; a second substrate that faces the first substrate; a liquid crystal layer that is located between the first substrate and the second substrate; and a first spacer that is located between the first substrate and the second substrate and is in contact with the first substrate, wherein the first substrate further comprises a second spacer that is located on the barrier layer and overlaps with the first spacer.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: May 21, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun Kim, Seul Ki Kim, Seung Ha Choi, Yun Seok Han, Kap Soo Yoon, Jeong Uk Heo
  • Patent number: 8604535
    Abstract: A non-volatile memory device includes an active region in which a channel of a transistor is formed in a substrate, element isolation films defining the active region and formed on the substrate at both sides of the channel at a height lower than an upper surface of the active region, a first dielectric layer, a second dielectric layer, and a control gate electrode formed on the active region in this order, and a floating gate electrode formed between the first dielectric layer and the second dielectric layer so as to intersect the length direction of the channel and extend to the upper surfaces of the element isolation films at both sides of the channel, thereby surrounding the channel.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: December 10, 2013
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Tea-Kwang Yu, Jeong-Uk Han, Yong-Tae Kim
  • Patent number: 8404542
    Abstract: A semiconductor device includes transistors with a vertical gate electrode. In a transistor structure, a semiconductor pattern has first and second sides facing in a transverse direction, and third and fourth sides facing in a longitudinal direction. Gate patterns are disposed adjacent to the first and second sides of the semiconductor pattern. Impurity patterns directly contact the third and fourth sides of the semiconductor pattern. A gate insulating pattern is interposed between the gate patterns and the semiconductor pattern.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: March 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Woo Kang, Jeong-Uk Han, Yong-Tae Kim, Seung-Beom Yoon
  • Patent number: 8362545
    Abstract: The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: January 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tea-Kwang Yu, Jeong-Uk Han, Yong-Tae Kim
  • Patent number: 8318583
    Abstract: Provided is a method of forming an isolation structure of a semiconductor device capable of minimizing the number of performing a patterning process and having trenches of various depths. The method includes partially etching the semiconductor substrate using a first patterning process to form first trenches and second trenches having a first depth. The semiconductor substrate has first to third regions. The first trenches are formed in the first region, and the second trenched are formed in the second region. The semiconductor substrate is partially etched using a second patterning process, so that third trenches are formed in the third region, and fourth trenches are formed in the second region. The fourth trenches extend from bottoms of the second trenches. The third trenches have a second depth, and the fourth trenches have a third depth. An isolation layer filling the first to fourth trenches is formed.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: November 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Sik Jeong, Jeong-Uk Han, Weon-Ho Park, Byung-Sup Shim
  • Publication number: 20120068249
    Abstract: The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer.
    Type: Application
    Filed: March 21, 2011
    Publication date: March 22, 2012
    Inventors: Tea-Kwang Yu, Jeong-Uk Han, Yong-Tae Kim
  • Patent number: 8097913
    Abstract: An electrically erasable and programmable read only memory (EEPROM) device and a method of manufacturing the EEPROM device are provided. First and second gate structures having the same structure are formed on a tunnel insulating layer formed on a substrate, such that the first and second gate structures are spaced apart from each other. A common source region is formed at a portion of the substrate located between the first and second gate structures. First and second drain regions are formed at first and second portions of the substrate adjacent to the first and second gate structures, respectively. Thus, the EEPROM device is manufactured including first and second transistors that have the same structure and may alternately serve as a memory transistor and a selection transistor according to an applied signal.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: January 17, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Weon-Ho Park, Jeong-Uk Han, Yong-Tae Kim
  • Patent number: 8059473
    Abstract: A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: November 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Seog Jeon, Seung-Beom Yoon, Jeong-Uk Han, Yong-Tae Kim
  • Patent number: 8053342
    Abstract: A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off-cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Kyu Lee, Jeong-Uk Han, Hee-Seog Jeon, Young-Ho Kim, Myung-Jo Chun, Jung-Ho Moon
  • Publication number: 20110175153
    Abstract: A semiconductor device includes transistors with a vertical gate electrode. In a transistor structure, a semiconductor pattern has first and second sides facing in a transverse direction, and third and fourth sides facing in a longitudinal direction. Gate patterns are disposed adjacent to the first and second sides of the semiconductor pattern. Impurity patterns directly contact the third and fourth sides of the semiconductor pattern. A gate insulating pattern is interposed between the gate patterns and the semiconductor pattern.
    Type: Application
    Filed: March 30, 2011
    Publication date: July 21, 2011
    Inventors: Sang-Woo Kang, Jeong-Uk Han, Yong-Tae Kim, Seung-Beom Yoon
  • Patent number: 7973314
    Abstract: A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers and by which the first and second circuits are electrically connected. One of the circuits is a logic circuit and the other of the circuits is a memory circuit. The semiconductor device is manufactured by fabricating transistors of the logic and memory circuits on respective substrates, stacking the substrates, and electrically connecting the logic and memory circuits with a via.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jin Yang, Jeong-Uk Han, Yong-Tae Kim, Yong-Suk Choi, Hyok-Ki Kwon
  • Patent number: 7944753
    Abstract: In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: May 17, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Kyu Lee, Jeong-Uk Han, Hee-Seog Jeon, Jung-Ho Moon, Soung-Youb Ha
  • Patent number: 7936003
    Abstract: A semiconductor device includes transistors with a vertical gate electrode. In a transistor structure, a semiconductor pattern has first and second sides facing in a transverse direction, and third and fourth sides facing in a longitudinal direction. Gate patterns are disposed adjacent to the first and second sides of the semiconductor pattern. Impurity patterns directly contact the third and fourth sides of the semiconductor pattern. A gate insulating pattern is interposed between the gate patterns and the semiconductor pattern.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: May 3, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Woo Kang, Jeong-Uk Han, Yong-Tae Kim, Seung-Beom Yoon
  • Patent number: 7932149
    Abstract: In a method of manufacturing a semiconductor device, a tunnel insulation layer is formed on a substrate. A charge trapping layer is formed on the tunnel insulation layer. A protection layer pattern or a mold is formed on the charge trapping layer. Charge trapping layer patterns are formed on the tunnel insulation layer by etching the charge trapping layer using the protection layer pattern or the mold. The charge trapping layer patterns may be spaced apart from each other. Blocking layers are formed on the charge trapping layer patterns, respectively. A gate electrode is formed on the blocking layers and the tunnel insulation layer using the protection layer pattern or the mold.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: April 26, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyun Park, Jeong-Uk Han, Jae-Min Yu, Young-Cheon Jeong, Sang-Hoon Park, Kwan-Jong Roh, Byeong-Cheol Lim, Yong-Seok Chung
  • Patent number: 7928492
    Abstract: A non-volatile memory integrated circuit device and a method fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, word and select lines, and a floating junction region, a bit line junction region and a common source region. The semiconductor substrate has a plurality of substantially rectangular field regions, and the short and long sides of each substantially rectangular field region are parallel to the row and column directions of a matrix, respectively.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: April 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-seog Jeon, Jeong-uk Han, Hyun-khe Yoo, Yong-kyu Lee
  • Publication number: 20110038210
    Abstract: In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.
    Type: Application
    Filed: October 26, 2010
    Publication date: February 17, 2011
    Inventors: Yong-Kyu Lee, Jeong-Uk Han, Hee-Seog Jeon, Jung-Ho Moon, Soung-Youb Ha
  • Patent number: 7855410
    Abstract: According to one embodiment, a semiconductor memory device can be generally characterized as including a gate insulating layer on a semiconductor substrate, a floating gate on the gate insulating layer and a word line disposed on one side of the floating gate. A first side of the floating gate facing the word line may include a projecting portion projecting toward the word line. A tip of the projecting portion may include a corner that extends substantially perpendicularly with respect to a top surface of the semiconductor substrate.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: December 21, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jin Yang, Jeong-Uk Han, Yong-Suk Choi, Hyok-Ki Kwon, Bae-Seong Kwon