Patents by Inventor JEONG HYEON PARK

JEONG HYEON PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11914001
    Abstract: A power control device configured for diagnosing an open-circuit fault occurring in a power system of an autonomous vehicle and an open-circuit diagnosis method thereof, may include a power control switch that selectively connects or separates main power output from the first power supply and auxiliary power output from the second power supply, and a processor that determines a possibility of an open-circuit fault of a vehicle power source based on a current flowing through the power control switch and determines whether it is possible to drive an electric load with an output power of the second power supply alone and determine an open-circuit position based on an output of the first power supply when there is the possibility of the open-circuit fault.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: February 27, 2024
    Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATION, YURA CORPORATION CO., LTD.
    Inventors: Soon Myung Kwon, Jung Hyeon Bae, Hyo Geun Kwak, Sae Rom Kim, Jeong Hyun Park, Young Hoo Yoon
  • Patent number: 11917907
    Abstract: The present disclosure relates to an organic electroluminescent device. The organic electroluminescent device of the present disclosure shows high luminous efficiency and good lifespan by comprising a specific combination of the plural kinds of host compounds and a specific hole transport compound.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: February 27, 2024
    Assignee: Rohm and Haas Electronic Materials Korea Ltd.
    Inventors: Kyoung-Jin Park, Tae-Jin Lee, Jae-Hoon Shim, Yoo Jin Doh, Hee-Choon Ahn, Young-Kwang Kim, Doo-Hyeon Moon, Jeong-Eun Yang, Su-Hyun Lee, Chi-Sik Kim, Ji-Song Jun
  • Publication number: 20230380254
    Abstract: A method for manufacturing a display device includes providing a donor substrate including a first base substrate and an organic material layer disposed on the first base substrate, etching the organic material layer to form an etched organic material layer using a laser device, providing a display substrate including a second base substrate and a plurality of first electrodes disposed on the second base substrate, aligning the donor substrate and the display substrate such that the etched organic material layer faces the plurality of first electrodes, and transferring the etched organic material layer to the display substrate using an energy generation device.
    Type: Application
    Filed: March 28, 2023
    Publication date: November 23, 2023
    Applicants: Samsung Display Co., Ltd., Postech Research and Business Development Foundation
    Inventors: Sungsoon IM, Jong Kyu KIM, Hyeon Woong HWANG, Jeong Hyeon PARK, Heemin PARK, Seungyong SONG, Duckjung LEE
  • Patent number: 11660068
    Abstract: A medical headgear includes an ultrasound transducer and a headgear. The ultrasound transducer is configured to generate a low intensity ultrasound. The headgear supports the ultrasound transducer. The headgear includes a rear portion case including a slide guide configured to support an occipital and a support pad configured to support a crown. The headgear further includes a front portion case connected to the rear portion case to be slidably movable in one direction. The front portion case includes two temporal support pads configured to support both temporal portions.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 30, 2023
    Assignee: NEUROSONA CO., LTD.
    Inventors: Ji Yeun Kim, Jeong Hyeon Park, Seoung Won Shin, Seung Schik Yoo
  • Patent number: 11447859
    Abstract: Provided are a novel metal triamine compound, a method for preparing the same, a composition for depositing a metal-containing thin film including the same, and a method for preparing a metal-containing thin film using the same. The metal triamine compound of the present invention has excellent reactivity, is thermally stable, has high volatility, and has high storage stability, and thus, it may be used as a metal-containing precursor to easily prepare a high-purity metal-containing thin film having high density.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: September 20, 2022
    Assignee: DNF CO., LTD.
    Inventors: Myong Woon Kim, Sang Ick Lee, Sang Jun Yim, Won Mook Chae, Jeong Hyeon Park, Kang Yong Lee, A Ra Cho, Joong Jin Park, Heang Don Lim
  • Publication number: 20210325787
    Abstract: Provided are an exposure apparatus including a light source unit which provides light for exposure and comprises micro light emitting diodes arranged in a matrix form; a substrate transfer unit which transfers a target substrate; and a control unit which controls at least one of the light source unit and the substrate transfer unit. The control unit allocates coordinates or an address to each micro light emitting diode and individually controls an amount of light of each micro light emitting diode according to a preset pattern based on the coordinates or the address.
    Type: Application
    Filed: November 19, 2020
    Publication date: October 21, 2021
    Inventors: Sung Soon IM, Jong Kyu KIM, Jeong Hyeon PARK, Seung Yong SONG, Duck Jung LEE, Jong Won LEE
  • Publication number: 20210222294
    Abstract: Provided are a novel metal triamine compound, a method for preparing the same, a composition for depositing a metal-containing thin film including the same, and a method for preparing a metal-containing thin film using the same. The metal triamine compound of the present invention has excellent reactivity, is thermally stable, has high volatility, and has high storage stability, and thus, it may be used as a metal-containing precursor to easily prepare a high-purity metal-containing thin film having high density.
    Type: Application
    Filed: April 26, 2018
    Publication date: July 22, 2021
    Applicant: DNF Co., Ltd.
    Inventors: Myong Woon KIM, Sang Ick LEE, Sang Jun YIM, Won Mook CHAE, Jeong Hyeon PARK, Kang Yong LEE, A Ra CHO, Joong Jin PARK, Heang Don LIM
  • Publication number: 20210017684
    Abstract: Disclosure relates to sewing machine capable of preventing thread cutting or deterioration caused by interference between leading end of needle and upper thread, that includes: head frame; needle bar supported on head frame to be movable up and down; needle having needle hole that penetrates in transverse direction with respect to axial line and has upper thread inserted thereinto and be coupled to lower end of needle bar to move up and down between lowered stitching position and lifted needle position; and presser foot unit having pressing part that is provided with needle guide hole through which needle passes and moves up and down between downward pressing height position where pressing part presses sewing material and lifting release height position where pressing part is lifted and spaced apart from sewing material and pressing foot arm that supports pressing part.
    Type: Application
    Filed: March 27, 2019
    Publication date: January 21, 2021
    Inventor: Jeong Hyeon PARK
  • Patent number: 10637467
    Abstract: A semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first gate insulator, a first source region and a first drain region, a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and a first gate electrode. The second transistor includes a second gate insulator, a second source region and a second drain region, a pair of drift regions that encompass the second source region and the second drain region respectively, and a second gate electrode, and the third transistor comprises a third gate insulator, a third source region and a third drain region, and a pair of drift regions that encompass the third source and the third drain regions respectively, and a third gate electrode. The second gate insulator is thinner than the other gate insulators.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 28, 2020
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Jeong Hyeon Park, Bo Seok Oh, Hee Hwan Ji
  • Publication number: 20200000428
    Abstract: Provided are a medical headgear which may be worn on a skull of an object while an ultrasound transducer is supported thereby, and the headgear according to an embodiment of the present disclosure may closely adhere and support an ultrasound transducer to the skull of the object regardless of the size and shape of the skull of the object and a position of the brain to which ultrasound needs to be transmitted. According to the medical headgear as described above, the ultrasound transducer supported on the headgear may be moved to a specific position on the skull, regardless of the position of the brain to which ultrasound needs to be transmitted, and thus, the use convenience of a user may be improved.
    Type: Application
    Filed: September 11, 2019
    Publication date: January 2, 2020
    Applicant: NEUROSONA CO., LTD.
    Inventors: Ji Yeun KIM, Jeong Hyeon PARK, Seoung Won SHIN, Seung Schik YOO
  • Patent number: 10504932
    Abstract: A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 10, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Bo Seok Oh, Hee Hwan Ji, Jeong Hyeon Park
  • Publication number: 20190028098
    Abstract: A semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first gate insulator, a first source region and a first drain region, a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and a first gate electrode. The second transistor includes a second gate insulator, a second source region and a second drain region, a pair of drift regions that encompass the second source region and the second drain region respectively, and a second gate electrode, and the third transistor comprises a third gate insulator, a third source region and a third drain region, and a pair of drift regions that encompass the third source and the third drain regions respectively, and a third gate electrode. The second gate insulator is thinner than the other gate insulators.
    Type: Application
    Filed: September 25, 2018
    Publication date: January 24, 2019
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Jeong Hyeon PARK, Bo Seok OH, Hee Hwan JI
  • Patent number: 10116305
    Abstract: A semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first gate insulator, a first source region and a first drain region, a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and a first gate electrode. The second transistor includes a second gate insulator, a second source region and a second drain region, a pair of drift regions that encompass the second source region and the second drain region respectively, and a second gate electrode, and the third transistor comprises a third gate insulator, a third source region and a third drain region, and a pair of drift regions that encompass the third source and the third drain regions respectively, and a third gate electrode. The second gate insulator is thinner than the other gate insulators.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 30, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Jeong Hyeon Park, Bo Seok Oh, Hee Hwan Ji
  • Publication number: 20180083043
    Abstract: A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.
    Type: Application
    Filed: November 30, 2017
    Publication date: March 22, 2018
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Bo Seok OH, Hee Hwan JI, Jeong Hyeon PARK
  • Publication number: 20180019262
    Abstract: A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.
    Type: Application
    Filed: March 6, 2017
    Publication date: January 18, 2018
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Bo Seok OH, Hee Hwan JI, Jeong Hyeon PARK
  • Patent number: 9871063
    Abstract: A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 16, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Bo Seok Oh, Hee Hwan Ji, Jeong Hyeon Park
  • Publication number: 20180013421
    Abstract: A semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first gate insulator, a first source region and a first drain region, a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and a first gate electrode. The second transistor includes a second gate insulator, a second source region and a second drain region, a pair of drift regions that encompass the second source region and the second drain region respectively, and a second gate electrode, and the third transistor comprises a third gate insulator, a third source region and a third drain region, and a pair of drift regions that encompass the third source and the third drain regions respectively, and a third gate electrode. The second gate insulator is thinner than the other gate insulators.
    Type: Application
    Filed: December 28, 2016
    Publication date: January 11, 2018
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Jeong Hyeon PARK, Bo Seok OH, Hee Hwan JI
  • Patent number: 8782902
    Abstract: A method of making a bearing includes providing a bearing intermediate, which is unfinished while having an overall shape of a finished bearing product; and repeatedly impacting a surface of the bearing intermediate at one or more ultrasonic frequencies to modify characteristics of the bearing intermediate. The resulting bearing intermediate or finished bearing product includes nano-size grains at or underneath the surface.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: July 22, 2014
    Assignee: Designmecha Co., Ltd.
    Inventors: Young Sik Pyun, Jeong Hyeon Park, Chang Sik Kim, In Ho Cho
  • Publication number: 20100024218
    Abstract: A method of making a bearing includes providing a bearing intermediate, which is unfinished while having an overall shape of a finished bearing product; and repeatedly impacting a surface of the bearing intermediate at one or more ultrasonic frequencies to modify characteristics of the bearing intermediate. The resulting bearing intermediate or finished bearing product includes nano-size grains at or underneath the surface.
    Type: Application
    Filed: October 13, 2009
    Publication date: February 4, 2010
    Applicant: DESIGNMECHA CO., LTD.
    Inventors: YOUNG SIK PYUN, JEONG HYEON PARK, CHANG SIK KIM, IN HO CHO