Abstract: A circuit for detecting leading or lagging phase relationship between first and second two-level input signals at each level transition of a selected one of the input signals and comprising first and second Exclusive OR gates each having first and second input terminals and a single output terminal and each responsive to signals of equal and non-equal logic levels supplied to the first and second input terminals thereof to produce an output signal having high and low logic levels, respectively. Further connections supply the first and second input signals to the first input terminal of the first and second Exclusive OR gates, respectively.

Abstract: A circuit for detecting leading or lagging phase relationship between first and second two-level input signals at each level transition of both of said input signals and comprising first and second voltage comparators each having first and second input terminals and a single output terminal and each responsive to signals of equal and non-equal logic levels supplied to the first and second input terminals thereof to produce an output signal having high and low logic levels, respectively. First and second input signals are supplied to the first input terminals of the first and second voltage comparators, respectively. A pulse generator responds to each level transition of said first input signal to produce a clock pulse.

Abstract: A circuit for determining each level transition of first and second two logic level input signals and their leading or lagging phase relationship at each level transition and comprising first and second signal level storage means each having first input means responsive to the first and second input signals, respectively, first output means, and clock input means and responsive to a clock signal supplied to the clock input means to cause the logic level on its output means to become equal to the logic level on its first input means. First and second Exclusive OR gates each have a first input means connected respectively to said first input means of said first and second signal level storage means, and a second input means connected respectively to said first output means of said first and second signal level storage means.

Abstract: A circuit for detecting each level transition of a first two-level signal of a given frequency and its leading or lagging phase relationship with a second two-level signal of said given frequency, and comprising signal level storage means having a data input terminal for receiving said first signal, a first output terminal, and a first clock pulse input terminal, and constructed to store the signal level supplied to its data input terminal and to transfer said stored signal level to its output terminal when a clock pulse is supplied to the clock pulse input terminal. First and second voltage comparator means each have a first input terminal for receiving said first and second signals, respectively, a second input terminal connected to said first output terminal and each constructed to respond to equal or non-equal signal levels supplied to their first and second input terminals to produce first and second input signals, respectively.

Abstract: An improvement to a pulse-echo ultrasonic-imaging system employing an acoustic focusing device occupying a fixed aperture to both illuminate internal structure of a visually opaque object with a scanning focused beam of ultrasonic energy and for returning a reflected signal portion of the scanning focused beam passed therethrough for detection. The improvement makes it possible to employ a large numerical aperture spherical lens exhibiting aberration as the focusing device by utilizing a corrector plate. The corrector plate causes the lens to image a flat transducer in a flat image field. Were it not for the corrector plate, the lens aberration would provide an undesired curved image field. The improved system is suitable for displaying deep soft tissue of a living human being for a medical diagnostic purpose.