Patents by Inventor Jeremy Kuehlwein
Jeremy Kuehlwein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11682437Abstract: A system includes a mixer of a phase interpolator. The mixer includes a dynamic load whose output signal is coupled to a subsequent stage of the phase interpolator. The dynamic load is configured to provide an alternating current (AC) signal to the subsequent stage of the phase interpolator as input clock signals. The mixer further includes a static load whose output signal is coupled to the subsequent stage of the phase interpolator in parallel with the respective output signal line of the dynamic load. The static load configured to provide a direct current (DC) signal to the phase interpolator temporarily in replacement of the respective AC signals to prevent output signals of the subsequent stage of the phase interpolator from being unpredictable.Type: GrantFiled: August 31, 2021Date of Patent: June 20, 2023Assignee: Micron Technology, Inc.Inventors: Steven G. Wurzer, Jeremy Kuehlwein, Michael J. O'Brien
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Publication number: 20230069329Abstract: A system includes a mixer of a phase interpolator. The mixer includes a dynamic load whose output signal is coupled to a subsequent stage of the phase interpolator. The dynamic load is configured to provide an alternating current (AC) signal to the subsequent stage of the phase interpolator as input clock signals. The mixer further includes a static load whose output signal is coupled to the subsequent stage of the phase interpolator in parallel with the respective output signal line of the dynamic load. The static load configured to provide a direct current (DC) signal to the phase interpolator temporarily in replacement of the respective AC signals to prevent output signals of the subsequent stage of the phase interpolator from being unpredictable.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Steven G. Wurzer, Jeremy Kuehlwein, Michael J. O'Brien
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Patent number: 11238006Abstract: According to one embodiment, an apparatus comprises a differential signaling bus, a tristate transmitter connected with the differential signaling bus, the tristate transmitter configured to provide a signal on the differential signaling bus responsive to a corresponding control signal, a receiver, a pair of differential inputs of the receiver connected with the differential signaling bus and configured to receive the signal from the differential signaling bus, and a termination circuit configured to couple a first differential input of the pair of differential inputs to a first voltage source and to couple a second differential input of the pair of differential inputs to a second voltage source, wherein the first and second voltage sources have different voltage levels.Type: GrantFiled: May 14, 2019Date of Patent: February 1, 2022Assignee: Micron Technology, Inc.Inventors: Jeremy Kuehlwein, Gregory King, Michael Stay
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Patent number: 10411916Abstract: Methods, systems, and devices for mitigating supply noise in single-ended current mode logic (CML) transmitters are described. A first current source may generate a first bias current for a first differential transistor pair included in a CML transmitter, and a second current source may generate a second bias current for a second differential transistor pair. The first differential transistor pair may route the first bias current through either leg of the first differential transistor pair based on a polarity of an input signal and the second differential transistor pair may route the second bias current through either leg of the second differential transistor pair based on the polarity of the input signal. Based on a first polarity, the second bias current may be routed to a ground reference, and based on a second polarity, the second bias current may be routed through the first differential transistor pair to modify a load current internal to the CML transmitter.Type: GrantFiled: February 28, 2019Date of Patent: September 10, 2019Assignee: Micron Technology, Inc.Inventors: Jeremy Kuehlwein, Gregory A. King
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Publication number: 20190266121Abstract: According to one embodiment, an apparatus comprises a differential signaling bus, a tristate transmitter connected with the differential signaling bus, the tristate transmitter configured to provide a signal on the differential signaling bus responsive to a corresponding control signal, a receiver, a pair of differential inputs of the receiver connected with the differential signaling bus and configured to receive the signal from the differential signaling bus, and a termination circuit configured to couple a first differential input of the pair of differential inputs to a first voltage source and to couple a second differential input of the pair of differential inputs to a second voltage source, wherein the first and second voltage sources have different voltage levels.Type: ApplicationFiled: May 14, 2019Publication date: August 29, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Jeremy Kuehlwein, Gregory King, Michael Stay
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Patent number: 10366041Abstract: According to one embodiment, an apparatus comprises a differential signaling bus, a tristate transmitter connected with the differential signaling bus, the tristate transmitter configured to provide a signal on the differential signaling bus responsive to a corresponding control signal, a receiver, a pair of differential inputs of the receiver connected with the differential signaling bus and configured to receive the signal from the differential signaling bus, and a termination circuit configured to couple a first differential input of the pair of differential inputs to a first voltage source and to couple a second differential input of the pair of differential inputs to a second voltage source, wherein the first and second voltage sources have different voltage levels.Type: GrantFiled: January 27, 2017Date of Patent: July 30, 2019Assignee: Micron Technology, Inc.Inventors: Jeremy Kuehlwein, Gregory King, Michael Stay
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Patent number: 10277426Abstract: Methods, systems, and devices for mitigating supply noise in single-ended current mode logic (CML) transmitters are described. A first current source may generate a first bias current for a first differential transistor pair included in a CML transmitter, and a second current source may generate a second bias current for a second differential transistor pair. The first differential transistor pair may route the first bias current through either leg of the first differential transistor pair based on a polarity of an input signal and the second differential transistor pair may route the second bias current through either leg of the second differential transistor pair based on the polarity of the input signal. Based on a first polarity, the second bias current may be routed to a ground reference, and based on a second polarity, the second bias current may be routed through the first differential transistor pair to modify a load current internal to the CML transmitter.Type: GrantFiled: August 27, 2018Date of Patent: April 30, 2019Assignee: Micron Technology, Inc.Inventors: Jeremy Kuehlwein, Gregory A. King
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Patent number: 10256998Abstract: Methods, systems, and devices for mitigating supply noise in single-ended current mode logic (CML) transmitters are described. A first current source may generate a first bias current for a first differential transistor pair included in a CML transmitter, and a second current source may generate a second bias current for a second differential transistor pair. The first differential transistor pair may route the first bias current through either leg of the first differential transistor pair based on a polarity of an input signal and the second differential transistor pair may route the second bias current through either leg of the second differential transistor pair based on the polarity of the input signal. Based on a first polarity, the second bias current may be routed to a ground reference, and based on a second polarity, the second bias current may be routed through the first differential transistor pair to modify a load current internal to the CML transmitter.Type: GrantFiled: May 3, 2018Date of Patent: April 9, 2019Assignee: Micron Technology, Inc.Inventors: Jeremy Kuehlwein, Gregory A. King
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Publication number: 20180217960Abstract: According to one embodiment, an apparatus comprises a differential signaling bus, a tristate transmitter connected with the differential signaling bus, the tristate transmitter configured to provide a signal on the differential signaling bus responsive to a corresponding control signal, a receiver, a pair of differential inputs of the receiver connected with the differential signaling bus and configured to receive the signal from the differential signaling bus, and a termination circuit configured to couple a first differential input of the pair of differential inputs to a first voltage source and to couple a second differential input of the pair of differential inputs to a second voltage source, wherein the first and second voltage sources have different voltage levels.Type: ApplicationFiled: January 27, 2017Publication date: August 2, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Jeremy Kuehlwein, Gregory King, Michael Stay
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Publication number: 20150333474Abstract: An apparatus with a differential impedance matched laser diode driver with AC-DC match.Type: ApplicationFiled: January 21, 2015Publication date: November 19, 2015Inventors: Raymond E. Barnett, Jeremy Kuehlwein, Douglas Dean
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Patent number: 7671667Abstract: One embodiment of the invention includes a current mirror system. The system comprises a master circuit configured to conduct a first current in response to an activation state of an activation signal. The system also comprises a slave circuit configured to generate at least one second additional current in response to the activation state of the activation signal. Each of the at least one additional current can be proportional to the first current. The system further comprises a current path circuit that is configured as a substantial copy of the master circuit, the current path circuit being configured to conduct the first current in response to a deactivation state of the activation signal.Type: GrantFiled: December 31, 2007Date of Patent: March 2, 2010Assignee: Texas Instruments IncorporatedInventors: Jeremy Kuehlwein, Marius Dina
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Patent number: 7206155Abstract: A write driver circuit (38) uses a matching resistors (R0, R1) to match the impedance of the head (32) disposed between output nodes (OUTP, OUTN). Control circuitry (Q4, Q5, Q6, Q7, R2, R4, R6 and R7) maintains the voltage at reference voltage nodes (VREFP, REFN) at essentially the same voltage as its corresponding output node. The matching resistor is disposed between the reference voltage node and the output node along with a driver (40a, 40b), which may be implemented as an AB driver. Since the voltage between the reference node and the output node is generally zero, very little current is shunted by the matching resistors, and thus, there is very little power wasted by the matching resistors. In the preferred embodiment, the output transistors of the AB drivers are driven by switched current sources (Q28 and Q29) to provide enhanced current to the bases of the output transistors on an as needed basis.Type: GrantFiled: September 30, 2004Date of Patent: April 17, 2007Assignee: Texas Instruments IncorporatedInventors: Jeremy Kuehlwein, Raymond E. Barnett
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Patent number: 7190541Abstract: A write driver (38) produces balanced voltages across head (32) by using the input write data (WDX and WDY) drive transistors of a slower transistor type (typically PNP) on one half of an H-bridge configuration, while transistors of a faster transistor type (typically NPN) in the other half of the H-bridge configuration are driven indirectly by transistors of the slower type, with a trans-resistance in series with transistors of the faster type. Accordingly, the voltage nodes on either side of the write head are pulled to Vcc and Vee symmetrically. A trans-resistance block (40) uses current sources to pull current from capacitive nodes for faster switching.Type: GrantFiled: March 14, 2006Date of Patent: March 13, 2007Assignee: Texas Instruments IncorporatedInventors: Jeremy Kuehlwein, Scott Sorenson
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Publication number: 20060171054Abstract: A write driver (38) produces balanced voltages across head (32) by using the input write data (WDX and WDY) drive transistors of a slower transistor type (typically PNP) on one half of an H-bridge configuration, while transistors of a faster transistor type (typically NPN) in the other half of the H-bridge configuration are driven indirectly by transistors of the slower type, with a trans-resistance in series with transistors of the faster type. Accordingly, the voltage nodes on either side of the write head are pulled to Vcc and Vee symmetrically. A trans-resistance block (40) uses current sources to pull current from capacitive nodes for faster switching.Type: ApplicationFiled: March 14, 2006Publication date: August 3, 2006Inventors: Jeremy Kuehlwein, Scott Sorenson
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Patent number: 7068454Abstract: A write driver produces balanced voltages across head by using the input write data drive transistors of a slower transistor type (typically PNP) on one half of an H-bridge configuration, while transistors of a faster transistor type (typically NPN) in the other half of the H-bridge configuration are driven indirectly by transistors of the slower type, with a trans-resistance in series with transistors of the faster type. Accordingly, the voltage nodes on either side of the write head are pulled to Vcc and Vee symmetrically. A trans-resistance block (40) uses current sources to pull current from capacitive nodes for faster switching.Type: GrantFiled: December 30, 2003Date of Patent: June 27, 2006Assignee: Texas Instruments IncorporatedInventors: Jeremy Kuehlwein, Scott Sorenson
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Publication number: 20060087761Abstract: A write driver output circuit having a programmable output impedance. A plurality of amplifiers are disposed in parallel between an input and an output of an impedance matching section of the write driver circuit and can be selectively enabled to correspondingly set the output impedance of the write driver circuit. The amplifiers may be Class AB amplifiers, each of which have a smaller size than an conventional AB used in a single amplifier write driver circuit. Each of the Class AB amplifiers has a corresponding matching resistor, and a current source, each being selectively enabled and disabled by enabling and disabling, respectively, the corresponding current sources, such as through the use of serial interface bits.Type: ApplicationFiled: October 26, 2004Publication date: April 27, 2006Inventor: Jeremy Kuehlwein
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Publication number: 20060044662Abstract: The present invention achieves technical advantages as a preamplifier write driver (10) having a varying common-mode output voltage. This varying common-mode output voltage also adjusts the derivative of the common-mode voltage, which is proportional to the amount of current coupled onto the MR head through parasitic capacitance. Currents of a first circuit (Q0,Q3) and a second circuit (Q1,Q2) are matched to overcome process variations and modeling errors. A pair of transresistance amplifiers (16) are driven by control lines (14) to achieve these matched currents.Type: ApplicationFiled: September 1, 2004Publication date: March 2, 2006Inventor: Jeremy Kuehlwein
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Publication number: 20050141120Abstract: A write driver (38) produces balanced voltages across head (32) by using the input write data (WDX and WDY) drive transistors of a slower transistor type (typically PNP) on one half of an H-bridge configuration, while transistors of a faster transistor type (typically NPN) in the other half of the H-bridge configuration are driven indirectly by transistors of the slower type, with a trans-resistance in series with transistors of the faster type. Accordingly, the voltage nodes on either side of the write head are pulled to Vcc and Vee symmetrically. A trans-resistance block (40) uses current sources to pull current from capacitive nodes for faster switching.Type: ApplicationFiled: December 30, 2003Publication date: June 30, 2005Applicant: Texas Instruments IncorporatedInventors: Jeremy Kuehlwein, Scott Sorenson
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Publication number: 20050105204Abstract: A fly height controller (10FHC; 10FHC?) for controlling the fly height of a read/write head assembly (15) in a disk drive (20) is disclosed. A heat element resistor (30) is disposed within the read/write head assembly (15). The fly height controller (10FHC; 10FHC?) includes registers (32R, 32W) for storing digital data words corresponding to the desired drive levels to be applied to the heat element resistor (30) during read and write operations. The registers (32R, 32W) are selectively coupled to a steady-state digital-to-analog converter (DAC) (36), depending upon whether a read or write operation is occurring; the output of the steady-state DAC (36) is applied to a voltage driver (40), which in turn drives current into the heat element resistor (30). Overdrive and underdrive transistors (44P, 44N) are provided to overdrive and underdrive the input to the voltage driver (40) in transitions between read and write operations.Type: ApplicationFiled: November 17, 2003Publication date: May 19, 2005Applicant: Texas Instruments IncorporatedInventors: Bryan Bloodworth, Congzhong Huang, Michael Sheperek, Jeremy Kuehlwein
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Publication number: 20050094305Abstract: A write driver circuit (38) uses a matching resistors (R0, R1) to match the impedance of the head (32) disposed between output nodes (OUTP, OUTN). Control circuitry (Q4, Q5, Q6, Q7, R2, R4, R6 and R7) maintains the voltage at reference voltage nodes (VREFP, REFN) at essentially the same voltage as its corresponding output node. The matching resistor is disposed between the reference voltage node and the output node along with a driver (40a, 40b), which may be implemented as an AB driver. Since the voltage between the reference node and the output node is generally zero, very little current is shunted by the matching resistors, and thus, there is very little power wasted by the matching resistors. In the preferred embodiment, the output transistors of the AB drivers are driven by switched current sources (Q28 and Q29) to provide enhanced current to the bases of the output transistors on an as needed basis.Type: ApplicationFiled: September 30, 2004Publication date: May 5, 2005Applicant: Texas Instruments IncorporatedInventors: Jeremy Kuehlwein, Raymond Barnett