Abstract: One illustrative device disclosed herein includes a transistor comprising a gate electrode and a drain region formed in a semiconducting substrate, an isolation structure formed in the substrate, wherein the isolation structure is laterally positioned between the gate electrode and the drain region, and a Faraday shield that is positioned laterally between the gate electrode and the drain region and above the isolation structure, wherein the Faraday shield has a long axis that is oriented substantially vertically relative to an upper surface of the substrate.

Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

Abstract: One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.

Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

Abstract: One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.

Abstract: A dielectric layer overlies a semiconductor substrate. The substrate has components and appropriate contacts formed therein. The dielectric layer electrically insulates the substrate and components from overlying conductive interconnect layers. A barrier layer is arranged over the dielectric layer to isolate the interconnect layers from other structures. A copper layer is then deposited over the barrier layer and thick interconnect lines having a first width and a first height are realized. Then, the barrier layer is etched using one of many alternative techniques. The barrier layer has a second width and a second height wherein the second width of the barrier liner is selected to be greater than the first width of the thick copper interconnect.

Abstract: One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.

Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

Abstract: One illustrative device includes a source region and a drain region formed in a substrate, wherein the source/drain regions are doped with a first type of dopant material, a gate structure positioned above the substrate that is laterally positioned between the source region and the drain region and a drain-side well region positioned in the substrate under a portion, but not all, of the entire lateral width of the drain region, wherein the drain-side well region is also doped with the first type of dopant material. The device also includes a source-side well region positioned in the substrate under an entire width of the source region and under a portion, but not all, of the drain region and a part of the extension portion of the drain region is positioned under a portion of the gate structure.

Abstract: One illustrative device disclosed herein includes a transistor comprising a gate electrode and a drain region formed in a semiconducting substrate, an isolation structure formed in the substrate, wherein the isolation structure is laterally positioned between the gate electrode and the drain region, and a Faraday shield that is positioned laterally between the gate electrode and the drain region and above the isolation structure, wherein the Faraday shield has a long axis that is oriented substantially vertically relative to an upper surface of the substrate.

Abstract: A semiconductor device is formed having compatibility with FINFET process flow, while having a large enough junction area of to reduce the discharge ESD current density. Embodiments include forming a removable gate over an N? doped fin on a substrate, forming P+ doped SiGe or Si on an anode side of the fin, and forming N+ doped Si on a cathode side of the fin. The area efficiency of the semiconductor device layout is greatly improved, and, thereby, discharge of ESD current density is mitigated.

Abstract: A semiconductor device is formed having compatibility with FINFET process flow, while having a large enough junction area of to reduce the discharge ESD current density. Embodiments include forming a removable gate over an N? doped fin on a substrate, forming P+ doped SiGe or Si on an anode side of the fin, and forming N+ doped Si on a cathode side of the fin. The area efficiency of the semiconductor device layout is greatly improved, and, thereby, discharge of ESD current density is mitigated.

Abstract: A dielectric layer overlies a semiconductor substrate. The substrate has components and appropriate contacts formed therein. The dielectric layer electrically insulates the substrate and components from overlying conductive interconnect layers. A barrier layer is arranged over the dielectric layer to isolate the interconnect layers from other structures. A copper layer is then deposited over the barrier layer and thick interconnect lines having a first width and a first height are realized. Then, the barrier layer is etched using one of many alternative techniques. The barrier layer has a second width and a second height wherein the second width of the barrier liner is selected to be greater than the first width of the thick copper interconnect.

Abstract: A method for manufacturing a DRAM cell including two active word lines having a drain region and distinct source regions, including, after the forming of insulated conductive lines, the steps of: depositing a first, then a second selectively etchable insulating layers; etching the second insulating layer to only maintain it above conductive lines; depositing and leveling a third insulating layer selectively etchable with respect to at least the second insulating layer; opening the first and third insulating layers to expose the drain region and an insulating trench; filling the previously-formed opening with a conductive material; polishing the entire structure; and depositing a fourth insulating layer, selectively etchable with respect to the third insulating layer.

Abstract: A capacitor having an electrode with a general cup shape, including a generally horizontal bottom and vertical walls, and in electric contact by its bottom with a conductive pad, the pad extending beyond the upper surface of an insulating layer and the bottom including a complementary recess of the protruding pad portion.

Abstract: A method for manufacturing a DRAM cell including two active word lines having a drain region and distinct source regions, including, after the forming of insulated conductive lines, the steps of: depositing a first, then a second selectively etchable insulating layers; etching the second insulating layer to only maintain it above conductive lines; depositing and leveling a third insulating layer selectively etchable with respect to at least the second insulating layer; opening the first and third insulating layers to expose the drain region and an insulating trench; filling the previously-formed opening with a conductive material; polishing the entire structure; and depositing a fourth insulating layer, selectively etchable with respect to the third insulating layer.

Abstract: A method of manufacturing DRAM cells in a substrate, including the steps of: depositing a first conductor in first openings in a first insulator partially exposing source/drain regions; opening a second insulator to partially expose the first openings contacting the source/drain regions, depositing a second conductor, then a third insulator, delimiting in the third insulator and second conductor bit lines of the memory cells, and forming lateral spacers on the sides of the bit lines; opening a fourth insulator to partially expose the first openings in contact with the drain/source regions of the transistors; depositing and etching a third conductor; conformally depositing a dielectric; and depositing a third conductor.