Abstract: A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.

Abstract: An electronic device, including: a plurality of contacts pads on a surface of a substrate; the contacts pads spaced apart a first predetermined distance in a first direction; and the contact pads spaced apart a second predetermined distance in a second direction, the first predetermined distance different from the second predetermined distance, the first direction perpendicular to the second direction.

Abstract: A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier. The carrier is formed of a flex material.

Abstract: An electronic device, including: a plurality of contacts pads on a surface of a substrate; the contacts pads spaced apart a first predetermined distance in a first direction; and the contact pads spaced apart a second predetermined distance in a second direction, the first predetermined distance different from the second predetermined distance, the first direction perpendicular to the second direction.

Abstract: A high efficiency two-part heat sink and air cooler apparatus or system for heat generating components, such as CPUs (central processing units) or the like electronic components. Moreover, there is also provided to a method of providing a high-efficiency heat sink and air cooling for the cooling of electronic components such as CPU units for processors, computers and diverse heat-generating devices.

Abstract: A high efficiency two-part heat sink and air cooler apparatus or system for heat generating components, such as CPUs (central processing units) or the like electronic components. Moreover, there is also provided to a method of providing a high-efficiency heat sink and air cooling for the cooling of electronic components such as CPU units for processors, computers and diverse heat-generating devices.

Abstract: A structure and associated method comprising contact pads on a surface of a substrate for coupling signal, power, and ground connections for an electrical device to a plurality of conductive wires on the substrate. The contact pads are formed in single lines along radial edges of sectors on the substrate. Each of the sectors comprise a predetermined angle between the radial edges of each of the sectors. The plurality of sectors collectively form a circular area. The contact pads comprise signal, power, and ground connections located at predetermined positions on the single lines along the radial edges of each of the sectors on the substrate.

Abstract: A simple, low-cost package consisting of a plurality of charge-coupled devices (CCD) having a transparent cover integrated to the CCDs is described. Interconnecting wires having a fine pitch are defined on the cover away from the light sensitive area of the CCDs to provide enhanced wiring capability. The cover is constructed on the same semiconductor wafer containing the CCDs, which are preferably arranged in a matrix formation, allowing the wafer to be diced into individual chips having any desired number of CCDs, all of which are protected by the integrated transparent cover facing the light sensitive surface of the CCDs. This structure has the further advantage of reducing defects by mounting the cover before dicing and handling the individual chips only after the cover window is already in place. Dicping width control is achieved using oxide trench as an etch channel.

Abstract: A simple, low-cost package consisting of a plurality of charge-coupled devices (CCD) having a transparent cover integrated to the CCDs is described. Interconnecting wires having a fine pitch are defined on the cover away from the light sensitive area of the CCDs to provide enhanced wiring capability. The cover is constructed on the same semiconductor wafer containing the CCDs, which are preferably arranged in a matrix formation, allowing the wafer to be diced into individual chips having any desired number of CCDs, all of which are protected by the integrated transparent cover facing the light sensitive surface of the CCDs. This structure has the further advantage of reducing defects by mounting the cover before dicing and handling the individual chips only after the cover window is already in place. Dicping width control is achieved using oxide trench as an etch channel.

Abstract: An integrated circuit assembly has pads of a chip electrically connected to pads of a substrate with rolling metal balls. A pliable material bonds the balls in movable contact with pads of the chip and substrate. Because the balls are relatively free to move, thermal expansion differences that would ordinarily cause enormous stresses in the attached joints of the prior art, simply cause rolling of the balls of the present invention, avoiding thermal stress altogether. Reliability of the connections is substantially improved as compared with C4 solder bumps, and chips can be safely directly mounted to such substrates as PC boards, despite substantial thermal mismatch.

Abstract: A method and structure for manufacturing Charge-Coupled-Device (CCD) image pick-up devices. The method bonds a first wafer with a second wafer. The first wafer has a CCD layer on a first substrate, wherein the CCD layer includes a plurality of CCD pick-up image arrays. The CCD layer is thin, preferably in a range of 5 to 20 microns, while the substrate is relatively thicker (e.g., 300 microns). The first wafer also includes first conductive pads arranged in a pattern on a surface of the CCD layer such that each CCD array is conductively coupled to a plurality of the first conductive pads. The second wafer has a second substrate that includes a semiconductor material such as silicon, and second conductive pads according to the pattern on a surface of the second substrate. The first wafer is bonded with the second wafer to form a wafer composite, wherein the first conductive pads are joined to the second conductive pads in accordance with the pattern.

Abstract: An integrated circuit assembly has pads of a chip electrically connected to pads of a substrate with rolling metal balls. A pliable material bonds the balls in movable contact with pads of the chip and substrate. Because the balls are relatively free to move, thermal expansion differences that would ordinarily cause enormous stresses in the attached joints of the prior art, simply cause rolling of the balls of the present invention, avoiding thermal stress altogether. Reliability of the connections is substantially improved as compared with C4 solder bumps, and chips can be safely directly mounted to such substrates as PC boards, despite substantial thermal mismatch.

Abstract: A printed circuit board is provided comprising a substrate, a conductor on the surface of the substrate, and an electronic component mounted on the conductor. The printed circuit board includes a first thermally conductive layer within the substrate and a second thermally conductive layer on a portion of the surface of the substrate and spaced from the electronic component. The electronic component is thermally coupled to the second thermally conductive layer by a thermally conductive aperture positioned within the substrate and connected to the conductor and the first thermally conductive layer. The first thermally conductive layer is connected to the second thermally conductive layer by a plurality of apertures also positioned in the substrate. Another printed circuit board is also provided comprising a first plurality of laminate dielectric layers, a conductor on a surface of the first plurality of laminated dielectric layers, and an electronic component mounted on the conductor.

Abstract: An integrated circuit assembly has pads of a chip electrically connected to pads of a substrate with rolling metal balls. A pliable material bonds the balls in movable contact with pads of the chip and substrate. Because the balls are relatively free to move, thermal expansion differences that would ordinarily cause enormous stresses in the attached joints of the prior art, simply cause rolling of the balls of the present invention, avoiding thermal stress altogether. Reliability of the connections is substantially improved as compared with C4 solder bumps, and chips can be safely directly mounted to such substrates as PC boards, despite substantial thermal mismatch.

Abstract: A simple and low cost ULSI integrated heatsink more efficiently removes heat from a silicon package by integrating the heat sink material into the silicon die, transforming the present two-dimensional art into three dimensions. The fabrication of a high power integrated ULSI package and heatsink begins by fabricating an integrated circuit wafer up to the point of dicing the wafer into individual chips. The front side of the wafer is protected, while the backside of the wafer is exposed. The exposed backside is roughened by chemical and/or mechanical process. Optionally, a gettering process is then performed to remove impurities. The roughened backside is then coated with metal interlayers, preferably aluminum (Al) by chromium (Cr). A layer of copper (Cu) is optionally coated on the metal interlayers. A highly conductive reflowable material, such as solder or gold eutectic, is deposited on the metal interlayers. At this point, the wafer is diced to form chips.

Abstract: A simple process for card assembly by Direct Chip Attachment (DCA) uses electrically conductive adhesives. Two methods create the same intermediate wafer product with a layer of insulative thermoplastic and conductive thermoplastic bumps. After sawing or dicing the wafer to form the chips, the chips are adhered to chip carriers with conductive pads which match the conductive thermoplastic bumps, using heat and pressure. Chips may be easily removed and replaced using heat.

Abstract: A simple and low cost ULSI integrated heatsink more efficiently removes heat from a silicon package by integrating the heat sink material into the silicon die, transforming the present two-dimensional art into three dimensions. The fabrication of a high power integrated ULSI package and heatsink begins by fabricating an integrated circuit wafer up to the point of dicing the wafer into individual chips. The front side of the wafer is protected, while the backside of the wafer is exposed. The exposed backside is roughened by chemical and/or mechanical process. Optionally, a gettering process is then performed to remove impurities. The roughened backside is then coated with metal interlayers, preferably aluminum (Al) followed by chromium (Cr). A layer of copper (Cu) is optionally coated on the metal interlayers. A highly conductive reflowable material, such as solder or gold eutectic, is deposited on the metal interlayers. At this point, the wafer is diced to form chips.

Abstract: A scanner using a small, inexpensive CCD array for accurately and easily re-creating an error free reproduction of any scanned image wherein a plurality of laser alignment marks are temporarily projected, from an inexpensive solid state laser via a low cost plastic fiber optic cable, onto the surface of the document, and capturing the image as a number of small segments, along both the horizontal and vertical dimensions of the document onto the surface of the image being scanned. These temporary, projected, alignment marks permit the accurate positioning of adjacent, scanned segments during reconstruction of the scanned document. This scanner can scan documents of any width with an accuracy such that the scanned document can be readily, easily and accurately reassembled regardless of the insensitivity of, or misalignment of the scanning array in the apparatus or the skew of the document relative to the camera doing the scanning.

Abstract: An electronic circuit package is fabricated by providing a substrate having attached to at least one of its major surfaces, at least one integrated circuit chip; and providing a carrier that comprises a polymeric composition. The carrier holds a desired array of conductive pins, which protrude from both major surfaces of the carrier. The substrate is placed in contact with the pins to provide a subassembly.

Abstract: A simple process for card assembly by Direct Chip Attachment (DCA) uses electrically conductive adhesives. Two methods create the same intermediate wafer product with a layer of insulative thermoplastic and conductive thermoplastic bumps. After sawing or dicing the wafer to form the chips, the chips are adhered to chip carriers with conductive pads which match the conductive thermoplastic bumps, using heat and pressure. Chips may be easily removed and replaced using heat.