Abstract: A system and method for generating a universal palette and for mapping the color space for an original image into the universal palette for compression. The universal palette utilizes a one byte three color format type allowing reservation of shades for a presentation layer of an operating system for the digital computer. The three color components for a pixel in an original image are then mapped to a specific palette having the one byte format. Mapping depends in part, upon the original component values. Where a color component does not correspond closely to a color component in the universal palette, it will have a value falling between first and second color values in the universal palette. The component is mapped to either the first or second color value on a pseudo-probablistic basis.

Abstract: Method and apparatus for converting multibit pixel data to a lesser number of bit pixel data and re-expanding the compressed data. Luminance data for each pixel is established as the 5 most significant bits of the original luminance signal. The chrominance information for groups of pixels is subsampled, and a common chrominance value assigned to each of the pixels in a group. The resulting compressed pixels may be 8 bits wide providing economical possibilities to store the 8 bit wide data. The data is expanded for display by adding lower order data bits to the compressed luminance signal data bits. A subsampled chrominance data signal is appended to the expanded luminance data for display.

Abstract: A digital display system includes a monitor arranged to receive digital display data and synchronizing signals to develop displays on a cathode ray tube. The monitor is switched between different line structure and/or color definition modes in response to the polarity of one of the vertical or horizontal synchronizing signals trains. A circuit receives this train to provide control signals to the horizontal time base and/or a color signal code converter. The time base control signal, in accordance with its binary value, controls the frequency of the time base. The color converter, in response to the control signals, either passes color signals received in parallel over six input lines without change to the cathode ray tube drive circuits or converts color signals on four of the input lines to output signals on the six lines to the drive circuits.

Abstract: In a bit mapped raster scan digital display system, a number of maps each contain a single component of the display data and are read together to provide sets of bytes, each set representing eight pel defining groups. A compare system is provided for determining when a pel group in a set of bytes compares with a reference pel defining group. For the, or each, pair of maps, the compare system compares all bits of the two bytes of data with the associated bit of the reference group to provide outputs when a corresponding bit in each of the bytes compares with the two reference bits. When more than two maps are employed the compare outputs related to all of the pairs of maps are combined to provide an output signal when a pel group in a byte from the maps compares with the reference bits. In a modification of the system the comparison can be made between one or more of the maps and the corresponding bit or bits of the compare data.

Abstract: A raster scan display system includes a plurality of storage maps. These maps are addressable in either of two modes. In the first mode each map contains bit mapped data and the maps are addressed together to provide color signals from which color video signals are derived. In the second mode, one map contains character representing data and a further map, character display dot patterns. In this mode the first map is addressed to provide partial addresses for the further map. These partial addresses are combined with row scan data signals to access the further map from which the character display dot data is used to generate the video signals.

Abstract: In a raster scan digital display system, a display image is stored, as coded characters or a bit map, which is larger than the display image. In order to define an image, within the stored image, for display, the addressing system for the memory (or memories) storing the image include a display image defining circuit. This circuit includes an address counter which is incremented to define successive addresses of data in a line of the displayed image, or row of characters therein. The circuit includes a first register to receive the initial address of a display image and a second register to receive a value indicating the width of the stored image. For the initial line (or character row) of a displayed image, the address counter is loaded from the first register and incremented from the initial address. For each subsequent line (or character row) the address from which the counter is incremented is the sum of the initial address of the previous line (or character row) and the value in the second register.

Abstract: Two controller units controlling a single input/output device such as a cathode ray tube (CRT) are synchronized by a command signal. Upon appearance of the command signal, the slave controller unit, which may have been running unsynchronized with the master controller, is stopped at the time for vertical retrace and remains stopped until vertical retrace time for the master controller. At this point, the slave controller is restarted in synchronism with the master controller and remains synchronized so long as both master and slave receive the same clock and the same screen refresh parameters.

Abstract: A serial keyboard interface (28) connects a self scanning programmable serialized keyboard (40) to the system bus (10) of a data processing system. A cable (42) containing only a clock wire (52) and a data wire (58) provides the connection. The keyboard transmits a 9-bit scan out code consisting of a start bit followed by eight serial data bits. The keyboard clock line (52) is connected to the clock or shift terminal of a serial-to-parallel shift register encoder (62) for shifting the data bits on data line (58) into the encoder which has eight parallel output data lines (A, B . . . G, H) connected to the system bus. When the encoder (62) contains a complete scan out frame, the start bit is in the most significant stage (h') and sets the D-type latch (68) to apply a CPU interrupt request to the system bus (10). At this time, the Q output of latch (68) pulls down the data line to ground potential, thereby disabling the data line and preventing further keyboard transmission of data.

Abstract: A 3.58 MHz subcarrier signal and a 14.318 MHz clock signal are applied to three flipflops (50, 52 and 54) in such a manner that there appears on the output terminals (Q and Q) of the latches individual phase-shifted subcarriers having relative phases of 0.degree., 180.degree., 90.degree., 270.degree., 135.degree. and 315.degree. , respectively, representing the colors yellow, blue, red, cyan, magenta and green, respectively. Computer-generated digital color signals (+BLUE, +GREEN, +RED) are applied to the switching inputs (A, B, C) of a multiplexer (56) in order selectively to switch to the output of the multiplexer individual ones of the phase-shifted subcarriers in accordance with the code represented by the digital color signals. The individual subcarriers are combined in a summing circuit (62, 64) with television synchronizing and blanking pulses to produce a composite video color signal which is directly compatible with a conventional composite monitor and, after R.F.

Abstract: A central processing unit (10) loads a border register (36) with four color bits representing digital color signals to be used in determining the color of only the border area (40) surrounding the video area (42) of a cathode ray tube display screen (44). A BORDER CONTROL TIME signal is generated at the appropriate times in the horizontal and vertical scanning periods of the cathode ray tube to apply the digital color border signals (R, G, G, I) to a composite video signal generator (38) which generates the composite video signal for a TV set (14) or a TV monitor.

Abstract: A digital display system includes a monitor arranged to receive digital display data and synchronizing signals to develop displays on a cathode ray tube. The monitor is switched between different line structure and/or color definition modes in response to the polarity of one of the vertical or horizontal synchronizing signals trains. A circuit receives this train to provide control signals to the horizontal time base and/or a color signal code converter. The time base control signal, in accordance with its binary value, controls the frequency of the time base. The color converter, in response to the control signals, either passes color signals received in parallel over six input lines without change to the cathode ray tube drive circuits or converts color signals on four of the input lines to output signals on the six lines to the drive circuits.