Patents by Inventor Jhy-Jyi Sze

Jhy-Jyi Sze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250048763
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 6, 2025
    Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Kuan-Chieh Huang, Jhy-Jyi Sze
  • Patent number: 12218171
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a first semiconductor substrate having a photodetector and a floating diffusion node. A transfer gate is disposed over the first semiconductor substrate, where the transfer gate is at least partially disposed between opposite sides of the photodetector. A second semiconductor substrate is vertically spaced from the first semiconductor substrate, where the second semiconductor substrate comprises a first surface and a second surface opposite the first surface. A readout transistor is disposed on the second semiconductor substrate, where the second surface is disposed between the transfer gate and a gate of the readout transistor. A first conductive contact is electrically coupled to the transfer gate and extending vertically from the transfer gate through both the first surface and the second surface.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Seiji Takahashi, Jhy-Jyi Sze
  • Patent number: 12211876
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varies at different heights along the side of the photodiode.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
  • Patent number: 12166054
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Kuan-Chieh Huang, Jhy-Jyi Sze
  • Publication number: 20240387587
    Abstract: A semiconductor image sensor includes a first substrate including a first front side and a first back side, and a second substrate including a second front side and a second back side. The first substrate includes a layer and a first light-sensing element in the layer. The layer includes a first semiconductor material, and the first light-sensing element includes a second semiconductor material. The second substrate is bonded to the first substrate with the second front side facing the first back side.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: JHY-JYI SZE, YI-SHIN CHU, YIN-KAI LIAO, HSIANG-LIN CHEN, SIN-YI JIANG, KUAN-CHIEH HUANG
  • Publication number: 20240387766
    Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: Jhy-Jyi Sze, Sin-Yi Jiang, Yi-Shin Chu, Yin-Kai Liao, Hsiang-Lin Chen, Kuan-Chieh Huang
  • Patent number: 12148782
    Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: November 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Chuang Wu, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Jhy-Jyi Sze, Keng-Yu Chou, Yen-Ting Chiang, Ming-Hsien Yang, Chun-Yuan Chen
  • Patent number: 12148853
    Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jhy-Jyi Sze, Sin-Yi Jiang, Yi-Shin Chu, Yin-Kai Liao, Hsiang-Lin Chen, Kuan-Chieh Huang
  • Publication number: 20240379720
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a first semiconductor substrate having a photodetector and a floating diffusion node. A transfer gate is disposed over the first semiconductor substrate, where the transfer gate is at least partially disposed between opposite sides of the photodetector. A second semiconductor substrate is vertically spaced from the first semiconductor substrate, where the second semiconductor substrate comprises a first surface and a second surface opposite the first surface. A readout transistor is disposed on the second semiconductor substrate, where the second surface is disposed between the transfer gate and a gate of the readout transistor. A first conductive contact is electrically coupled to the transfer gate and extending vertically from the transfer gate through both the first surface and the second surface.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Seiji Takahashi, Jhy-Jyi Sze
  • Publication number: 20240371900
    Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate. A grid structure extends from a first side of the semiconductor substrate to within the semiconductor substrate. An image sensing element is disposed within the semiconductor substrate and is laterally surrounded by the grid structure. A plurality of protrusions are arranged along the first side of the semiconductor substrate. The plurality of protrusions are disposed over the image sensing element and are laterally surrounded by the grid structure. The plurality of protrusions are substantially identical to one another and have a characteristic dimension. An inner surface of the grid structure facing the image sensing element is spaced apart from a point of one of the plurality of protrusions by a predetermined reflective length that is based on the characteristic dimension of the plurality of protrusions.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Chin-Chia Kuo, Jhy-Jyi Sze, Tung-Ting Wu, Yimin Huang
  • Publication number: 20240371904
    Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Wei Chuang Wu, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Jhy-Jyi Sze, Keng-Yu Chou, Yen-Ting Chiang, Ming-Hsien Yang, Chun-Yuan Chen
  • Patent number: 12136638
    Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate. A grid structure extends from a first side of the semiconductor substrate to within the semiconductor substrate. An image sensing element is disposed within the semiconductor substrate and is laterally surrounded by the grid structure. A plurality of protrusions are arranged along the first side of the semiconductor substrate. The plurality of protrusions are disposed over the image sensing element and are laterally surrounded by the grid structure. The plurality of protrusions are substantially identical to one another and have a characteristic dimension. An inner surface of the grid structure facing the image sensing element is spaced apart from a point of one of the plurality of protrusions by a predetermined reflective length that is based on the characteristic dimension of the plurality of protrusions.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: November 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chia Kuo, Jhy-Jyi Sze, Tung-Ting Wu, Yimin Huang
  • Publication number: 20240355953
    Abstract: A photovoltaic cell includes a germanium-containing well embedded in a single crystalline silicon substrate and extending to a proximal horizontal surface of the single crystalline silicon substrate, wherein germanium-containing well includes germanium at an atomic percentage greater than 50%. A silicon-containing capping structure is located on a top surface of the germanium-containing well and includes silicon at an atomic percentage greater than 42%. The silicon-containing capping structure prevents oxidation of the germanium-containing well. A photovoltaic junction may be formed within, or across, the trench by implanting dopants of a first conductivity type and dopants of a second conductivity type.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 24, 2024
    Inventors: Jyh-Ming HUNG, Tzu-Jui WANG, Kuan-Chieh HUANG, Jhy-Jyi SZE
  • Publication number: 20240332338
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a masking layer on a first side of a substrate. A first etching process is performed on the first side of the substrate with the masking layer in place. The masking layer is removed. A second wet etching process is performed on the first side of the substrate after removing the masking layer. The first etching process and the second wet etching process collectively form a plurality of topographical features respectively having a triangular shape in a cross-section.
    Type: Application
    Filed: June 12, 2024
    Publication date: October 3, 2024
    Inventors: Tung-Ting Wu, Jhy-Jyi Sze, Yimin Huang
  • Patent number: 12100726
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate. One or more isolation structures are arranged within one or more trenches in the semiconductor substrate. The one or more trenches are disposed along opposing sides of a photo diode region within the semiconductor substrate. The semiconductor substrate includes an undulating exterior having rounded corners arranged laterally between neighboring ones of a plurality of flat surfaces. The rounded corners and the plurality of flat surfaces forming a plurality of triangular shaped protrusions arranged between the one or more isolation structures, as viewed along a cross-sectional view.
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: September 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ting Wu, Jhy-Jyi Sze, Yimin Huang
  • Publication number: 20240313010
    Abstract: In some embodiments, the present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a floating diffusion node disposed within a substrate. A plurality of photodetectors are disposed around the floating diffusion node, as viewed in a plan-view, and a plurality of transfer transistor gates are disposed between the floating diffusion node and the plurality of photodetectors, as viewed in the plan-view. One or more transistor gates are disposed on the substrate. A device isolation structure extends in a closed loop around the one or more transistor gates. The device isolation structure is laterally offset from the floating diffusion node.
    Type: Application
    Filed: May 31, 2024
    Publication date: September 19, 2024
    Inventors: Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Feng-Chi Hung, Feng-Jia Shiu, Jen-Cheng Liu, Jhy-Jyi Sze, Chun-Wei Chang, Wei-Cheng Hsu, Wei Chuang Wu, Yimin Huang
  • Publication number: 20240282797
    Abstract: The present disclosure relates to a CMOS image sensor. The image sensor comprises a pixel region comprising a photodiode disposed within a substrate. A deep trench isolation (DTI) ring encloses the photodiode from top view and extends from a back-side to a first position within the substrate from cross-sectional view. A pair of shallow trench isolation (STI) structures is respectively disposed at an inner periphery and an outer periphery sandwiching the DTI ring from top view and extends from a front-side to a second position within the substrate from cross-sectional view. A pixel device is disposed at the front-side of the substrate directly overlying the DTI ring. The pixel device comprises a gate electrode disposed over the substrate and a pair of source/drain (S/D) regions disposed within the substrate and reaching on a top surface of the DTI ring.
    Type: Application
    Filed: April 17, 2024
    Publication date: August 22, 2024
    Inventors: Seiji Takahashi, Jhy-Jyi Sze, Tzu-Hsiang Chen
  • Patent number: 12051763
    Abstract: A photovoltaic cell includes a germanium-containing well embedded in a single crystalline silicon substrate and extending to a proximal horizontal surface of the single crystalline silicon substrate, wherein germanium-containing well includes germanium at an atomic percentage greater than 50%. A silicon-containing capping structure is located on a top surface of the germanium-containing well and includes silicon at an atomic percentage greater than 42%. The silicon-containing capping structure prevents oxidation of the germanium-containing well. A photovoltaic junction may be formed within, or across, the trench by implanting dopants of a first conductivity type and dopants of a second conductivity type.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jyh-Ming Hung, Tzu-Jui Wang, Kuan-Chieh Huang, Jhy-Jyi Sze
  • Patent number: 12040336
    Abstract: In some embodiments, the present disclosure relates to method for forming an image sensor integrated chip. The method includes forming a first photodetector region in a substrate and forming a second photodetector region in the substrate. A floating diffusion node is formed in the substrate between the first photodetector region and the second photodetector region. A pick-up well contact region is formed in the substrate. A first line intersects the floating diffusion node and the pick-up well contact region. One or more transistor gates are formed on the substrate. A second line that is perpendicular to the first line intersects the pick-up well contact region and the one or more transistor gates.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Feng-Chi Hung, Feng-Jia Shiu, Jen-Cheng Liu, Jhy-Jyi Sze, Chun-Wei Chang, Wei-Cheng Hsu, Wei Chuang Wu, Yimin Huang
  • Publication number: 20240204016
    Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.
    Type: Application
    Filed: February 29, 2024
    Publication date: June 20, 2024
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Hsiao-Hui Tseng, Jen-Cheng Liu, Jhy-Jyi Sze, Shyh-Fann Ting, Wei Chuang Wu, Yen-Ting Chiang, Chia Ching Liao, Yen-Yu Chen