Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of memory cells. The controller is configured to select first map data entries associated with first data entries stored in a first region of the memory device that includes some of the plurality of memory cells, to exclude a second map data entry associated with second data entry sequentially read from among the first map data entries, and to transmit a remaining first map data entry to an external device.

Abstract: A storage device includes: a nonvolatile memory device; a volatile memory device including: a map data storage for temporarily storing a part of map data representing a relationship between a logical address of data, provided from a host device, and a physical address corresponding to a position in the nonvolatile memory device in which the data is stored; and a prefetch data storage for storing, as prefetch data, map data about at least two logical addresses prefetched from the host device; and a memory controller for controlling the nonvolatile memory device and the volatile memory device to process a multi-chunk read command as a read request for the at least two logical addresses received from the host device by using the prefetch data, and maintain the prefetch data in the prefetch data storage.

Abstract: An operation method of a controller for controlling a memory device includes: queuing an identifier of a logical address region associated with a read request from a host in a most recently used (MRU) entry of an internal logical address region queue; increasing a weighted value for a read count of the logical address region by a first value according to whether the identifier of the logical address region has been queued in the logical address region queue before being queued in the MRU entry; adding the weighted value to the read count of the logical address region; providing the host with a map segment corresponding to the logical address region according to a threshold of the read count; and controlling a read operation of the memory device based on a physical address according to whether the read request includes the physical address.

Abstract: A computing system includes a host and a storage device. The host includes a host memory, and the storage device includes a processor, a semiconductor memory device and a device memory which caches mapping information of the semiconductor memory device. In operation, the processor transmits to the host read data and mapping table entry information of a logical address region corresponding to the read data in response to a read request. The mapping table entry information is transmitted to the host based on features of the logical address region. Additionally, the host may transmit a read buffer request corresponding to the mapping table entry information to the storage device, and the storage device may transmit mapping information corresponding to the read buffer request to the host, which then stores the mapping information in the host memory.

Abstract: A storage device communicates with a host including a host memory. The storage device includes a semiconductor memory device and a device memory. The semiconductor memory device includes a plurality of non-volatile memory cells. The device memory stores validity information of host performance booster (HPB) sub-regions included in each of HPB regions cached in the host memory. The storage device determines to deactivate at least one HPB region among the HPB regions cached in the host memory based on the validity information included in the device memory, and transfers a message recommending to deactivate the determined HPB region to the host.

Abstract: A storage device communicates with a host including a host memory. The storage device includes a semiconductor memory device and a device memory. The semiconductor memory device includes a plurality of non-volatile memory cells. The device memory stores validity information of host performance booster (HPB) sub-regions included in each of HPB regions cached in the host memory. The storage device determines to deactivate at least one HPB region among the HPB regions cached in the host memory based on the validity information included in the device memory, and transfers a message recommending to deactivate the determined HPB region to the host.

Abstract: An operation method of a controller for controlling a memory device includes: queuing an identifier of a logical address region associated with a read request from a host in a most recently used (MRU) entry of an internal logical address region queue; increasing a weighted value for a read count of the logical address region by a first value according to whether the identifier of the logical address region has been queued in the logical address region queue before being queued in the MRU entry; adding the weighted value to the read count of the logical address region; providing the host with a map segment corresponding to the logical address region according to a threshold of the read count; and controlling a read operation of the memory device based on a physical address according to whether the read request includes the physical address.

Abstract: A computing system includes a host and a storage device. The host includes a host memory, and the storage device includes a processor, a semiconductor memory device and a device memory which caches mapping information of the semiconductor memory device. In operation, the processor transmits to the host read data and mapping table entry information of a logical address region corresponding to the read data in response to a read request. The mapping table entry information is transmitted to the host based on features of the logical address region. Additionally, the host may transmit a read buffer request corresponding to the mapping table entry information to the storage device, and the storage device may transmit mapping information corresponding to the read buffer request to the host, which then stores the mapping information in the host memory.