Abstract: A method for manufacturing a gas diffusion layer for a fuel cell wherein carbon nanotubes are impregnated into Korean paper, thereby enhancing electroconductivity, and a gas diffusion layer manufactured thereby. The method for manufacturing a gas diffusion layer for a fuel cell which is to manufacture a gas diffusion layer as a constituent member of a unit cell in a fuel cell, includes a support preparation step of preparing a support with Korean paper; a dispersion preparation step of dispersing a carbon substance in a solvent to form a dispersion, a coating step of coating the support with the dispersion, and a thermal treatment step of thermally treating the dispersion-coated support to fix the carbon substance to the support.

Abstract: A semiconductor package includes a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern; a first semiconductor chip placed on an upper surface of the first substrate; a ball array structure that is placed on the upper surface of the first substrate along a perimeter of the first semiconductor chip and is electrically connected to the ground pattern; and a shielding structure placed on the upper surface of the first semiconductor chip and in contact with the upper surface of the ball array structure. The ball array structure has a closed loop shape, and includes a solder ball portion and a connecting portion that connects adjacent solder ball portions. A maximum width of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion.

Abstract: Provided is a semiconductor package comprising a lower package that includes a lower substrate and a lower semiconductor chip, an interposer substrate on the lower package and having a plurality of holes that penetrate the interposer substrate, a thermal radiation structure that includes a supporter on a top surface of the interposer substrate and a plurality of protrusions in the holes of the interposer substrate, and a thermal conductive layer between the lower semiconductor chip and the protrusions of the thermal radiation structure.

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

Abstract: A semiconductor package includes: a lower package: an upper substrate on the lower package: and connection members connecting the lower package to the upper substrate, wherein the lower package includes: a lower substrate; and a lower semiconductor chip, wherein the upper substrate includes: an upper substrate body: upper connection pads combined with the connection members: and auxiliary members extending from the upper substrate body toward the lower substrate, wherein the connection members are arranged in a first horizontal direction to form a first connection member column, wherein the auxiliary members are arranged in the first horizontal direction to form a first auxiliary member column, wherein the first connection member column and the first auxiliary member column are located between a side surface of the lower semiconductor chip and a side surface of the lower substrate, and the first auxiliary member column is spaced apart from the first connection member column.

Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.

Abstract: A semiconductor package includes a first wiring structure which includes a first insulating layer, and a first wiring pad inside the first insulating layer, a first semiconductor chip on the first wiring structure, a second wiring structure on the first semiconductor chip, and a connecting member between the first wiring structure and the second wiring structure. The second wiring structure includes a second insulating layer and a plurality of second wiring pads in the second insulating layer which each directly contact one surface of the first semiconductor chip.

Abstract: A semiconductor package is provided. A semiconductor package includes a wiring structure, which includes a first insulating layer and a first wiring pad inside the first insulating layer a semiconductor chip on the wiring structure, an interposer having one surface facing the semiconductor chip and including a second insulating layer and a second wiring pad inside the second insulating layer, a connecting member connecting the first wiring pad and the second wiring pad, a support member in the first recess and between the wiring structure and the interposer, and a mold layer covering the semiconductor chip. One surface of the wiring structure includes a first recess exposing at least a part of the first insulating layer.

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

Abstract: A semiconductor package device may include a first package substrate, a first semiconductor chip on the first package substrate, an interposer on the first semiconductor chip, a warpage prevention member on the interposer, a molding member on the interposer and the first package substrate, and a second package substrate on the molding member. At least a portion of a top surface of the molding member may be spaced apart from a bottom surface of the second package substrate.

Abstract: Provided is a semiconductor package comprising a lower package that includes a lower substrate and a lower semiconductor chip, an interposer substrate on the lower package and having a plurality of holes that penetrate the interposer substrate, a thermal radiation structure that includes a supporter on a top surface of the interposer substrate and a plurality of protrusions in the holes of the interposer substrate, and a thermal conductive layer between the lower semiconductor chip and the protrusions of the thermal radiation structure.

Abstract: A semiconductor package includes a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern; a first semiconductor chip placed on an upper surface of the first substrate; a ball array structure that is placed on the upper surface of the first substrate along a perimeter of the first semiconductor chip and is electrically connected to the ground pattern; and a shielding structure placed on the upper surface of the first semiconductor chip and in contact with the upper surface of the ball array structure. The ball array structure has a closed loop shape, and includes a solder ball portion and a connecting portion that connects adjacent solder ball portions. A maximum width of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion.

Abstract: A semiconductor package includes: a lower package: an upper substrate on the lower package: and connection members connecting the lower package to the upper substrate. wherein the lower package includes: a lower substrate; and a lower semiconductor chip, wherein the upper substrate includes: an upper substrate body: upper connection pads combined with the connection members: and auxiliary members extending from the upper substrate body toward the lower substrate, wherein the connection members are arranged in a first horizontal direction to form a first connection member column, wherein the auxiliary members are arranged in the first horizontal direction to form a first auxiliary member column, wherein the first connection member column and the first auxiliary member column are located between a side surface of the lower semiconductor chip and a side surface of the lower substrate, and the first auxiliary member column is spaced apart from the first connection member column.

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.