Patents by Inventor Ji Hwang Kim
Ji Hwang Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240363472Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.Type: ApplicationFiled: July 10, 2024Publication date: October 31, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Ji Hwang KIM, Jong Bo SHIM, Jang Woo LEE, Yung Cheol KONG, Young Hoon HYUN
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Patent number: 12113087Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.Type: GrantFiled: March 28, 2023Date of Patent: October 8, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-hwang Kim, Jong-bo Shim, Sang-uk Han, Cha-jea Jo, Won-il Lee
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Publication number: 20240332270Abstract: The present disclosure relates to semiconductor packages and methods for manufacturing semiconductor packages. An example semiconductor package includes a top die, first and second bottom dies attached on a lower surface of the top die and being apart from each other by a preset distance, and at least one decoupling capacitor connected to the lower surface of the top die between the first bottom die and the second bottom die. The top die, the first bottom die, and the second bottom die are chiplets.Type: ApplicationFiled: September 27, 2023Publication date: October 3, 2024Inventors: Sangjin Baek, Kyung Don Mun, Ji Hwang Kim, Kyoung Lim Suk
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Patent number: 12065604Abstract: A quantum dot composite that includes a matrix; and a plurality of quantum dots and titanium oxide particles dispersed in the matrix, wherein the quantum dots include zinc, tellurium, and selenium, the quantum dots do not comprise cadmium, lead, mercury, or a combination thereof, and in the quantum dot composite, a weight ratio of tellurium with respect to titanium is greater than or equal to about 1.5:1 and less than or equal to about 10:1.Type: GrantFiled: October 15, 2021Date of Patent: August 20, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Soo Kyung Kwon, Yong Wook Kim, Ji-Yeong Kim, Seon-Yeong Kim, Sungwoo Hwang
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Patent number: 12062605Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.Type: GrantFiled: April 27, 2023Date of Patent: August 13, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hwang Kim, Hyunkyu Kim, Jongbo Shim, Eunhee Jung, Kyoungsei Choi
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Patent number: 12057366Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.Type: GrantFiled: March 3, 2023Date of Patent: August 6, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Hwang Kim, Jong Bo Shim, Jang Woo Lee, Yung Cheol Kong, Young Hoon Hyun
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Publication number: 20240243053Abstract: A semiconductor package includes a first redistribution layer; a first semiconductor chip above the first redistribution layer; a second semiconductor chip above the first semiconductor chip; a second redistribution layer above the second semiconductor chip; a first connection structure on the second redistribution layer; a connection post on the first connection structure; and a connection interconnection layer on the connection post, wherein the connection interconnection layer comprises a connection insulating layer and a connection via extending through the connection insulating layer, and wherein the second redistribution layer and the first redistribution layer are electrically connected to each other through a wire.Type: ApplicationFiled: August 29, 2023Publication date: July 18, 2024Inventors: JI HWANG KIM, JOONSUNG KIM, SANGJIN BAEK, KYOUNG LIM SUK
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Publication number: 20240178114Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a lower semiconductor chip on a first redistribution substrate and including a through via, a lower molding layer on the first redistribution substrate and surrounding the lower semiconductor chip, a lower post on the first redistribution substrate and laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and coupled to the through via, an upper molding layer on the lower molding layer and surrounding the upper semiconductor chip, an upper post on the lower molding layer and laterally spaced apart from the upper semiconductor chip, and a second redistribution substrate on the upper molding layer and coupled to the upper post. A top surface of the lower molding layer is at a level higher than that of a top surface of the lower semiconductor chip.Type: ApplicationFiled: July 28, 2023Publication date: May 30, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: KYOUNG LIM SUK, DONGKYU KIM, JI HWANG KIM, HYEONJEONG HWANG
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Patent number: 11908806Abstract: A semiconductor package includes a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern; a first semiconductor chip placed on an upper surface of the first substrate; a ball array structure that is placed on the upper surface of the first substrate along a perimeter of the first semiconductor chip and is electrically connected to the ground pattern; and a shielding structure placed on the upper surface of the first semiconductor chip and in contact with the upper surface of the ball array structure. The ball array structure has a closed loop shape, and includes a solder ball portion and a connecting portion that connects adjacent solder ball portions. A maximum width of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion.Type: GrantFiled: October 14, 2021Date of Patent: February 20, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong Ho Kim, Ji Hwang Kim, Hwan Pil Park, Jong Bo Shim
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Patent number: 11876083Abstract: Provided is a semiconductor package comprising a lower package that includes a lower substrate and a lower semiconductor chip, an interposer substrate on the lower package and having a plurality of holes that penetrate the interposer substrate, a thermal radiation structure that includes a supporter on a top surface of the interposer substrate and a plurality of protrusions in the holes of the interposer substrate, and a thermal conductive layer between the lower semiconductor chip and the protrusions of the thermal radiation structure.Type: GrantFiled: August 20, 2021Date of Patent: January 16, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Dongho Kim, Ji Hwang Kim, Hwan Pil Park, Jongbo Shim
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Publication number: 20230260891Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.Type: ApplicationFiled: April 27, 2023Publication date: August 17, 2023Inventors: JI HWANG KIM, HYUNKYU KIM, JONGBO SHIM, EUNHEE JUNG, KYOUNGSEL CHOI
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Patent number: 11728230Abstract: A semiconductor package includes: a lower package: an upper substrate on the lower package: and connection members connecting the lower package to the upper substrate, wherein the lower package includes: a lower substrate; and a lower semiconductor chip, wherein the upper substrate includes: an upper substrate body: upper connection pads combined with the connection members: and auxiliary members extending from the upper substrate body toward the lower substrate, wherein the connection members are arranged in a first horizontal direction to form a first connection member column, wherein the auxiliary members are arranged in the first horizontal direction to form a first auxiliary member column, wherein the first connection member column and the first auxiliary member column are located between a side surface of the lower semiconductor chip and a side surface of the lower substrate, and the first auxiliary member column is spaced apart from the first connection member column.Type: GrantFiled: June 17, 2021Date of Patent: August 15, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hwang Kim, Dongho Kim, Jin-Woo Park, Jongbo Shim
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Publication number: 20230238417Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.Type: ApplicationFiled: March 28, 2023Publication date: July 27, 2023Inventors: Ji-hwang KIM, Jong-bo SHIM, Sang-uk HAN, Cha-jea JO, Won-il LEE
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Publication number: 20230207416Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.Type: ApplicationFiled: March 3, 2023Publication date: June 29, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Ji Hwang KIM, Jong Bo Shim, Jang Woo Lee, Yung Cheol Kong, Young Hoon Hyun
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Patent number: 11658107Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.Type: GrantFiled: June 21, 2022Date of Patent: May 23, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hwang Kim, Hyunkyu Kim, Jongbo Shim, Eunhee Jung, Kyoungsei Choi
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Patent number: 11637140Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.Type: GrantFiled: March 16, 2021Date of Patent: April 25, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-hwang Kim, Jong-bo Shim, Sang-uk Han, Cha-jea Jo, Won-il Lee
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Publication number: 20230111343Abstract: A semiconductor package includes a first wiring structure which includes a first insulating layer, and a first wiring pad inside the first insulating layer, a first semiconductor chip on the first wiring structure, a second wiring structure on the first semiconductor chip, and a connecting member between the first wiring structure and the second wiring structure. The second wiring structure includes a second insulating layer and a plurality of second wiring pads in the second insulating layer which each directly contact one surface of the first semiconductor chip.Type: ApplicationFiled: October 7, 2022Publication date: April 13, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Choong Bin YIM, Ji Hwang KIM, Jin-woo PARK, Jong Bo SHIM
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Publication number: 20230076184Abstract: A semiconductor package is provided. A semiconductor package includes a wiring structure, which includes a first insulating layer and a first wiring pad inside the first insulating layer a semiconductor chip on the wiring structure, an interposer having one surface facing the semiconductor chip and including a second insulating layer and a second wiring pad inside the second insulating layer, a connecting member connecting the first wiring pad and the second wiring pad, a support member in the first recess and between the wiring structure and the interposer, and a mold layer covering the semiconductor chip. One surface of the wiring structure includes a first recess exposing at least a part of the first insulating layer.Type: ApplicationFiled: July 28, 2022Publication date: March 9, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Jong Bo SHIM, Sung Bum KIM, Ji Hwang KIM
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Patent number: 11600545Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.Type: GrantFiled: July 15, 2021Date of Patent: March 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Hwang Kim, Jong Bo Shim, Jang Woo Lee, Yung Cheol Kong, Young Hoon Hyun
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Patent number: 11569201Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.Type: GrantFiled: October 25, 2021Date of Patent: January 31, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Hyoeun Kim, Ji Hwang Kim, Jisun Yang, Seunghoon Yeon, Chajea Jo, Sang-Uk Han