Patents by Inventor Jisoo Hwang

Jisoo Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11830813
    Abstract: A semiconductor chip includes a first core region including a first core and a first power line configured to provide a first voltage to the first core, a second core region including a second core and a second power line configured to provide the first voltage to the second core, a cache region between the first core region and the second core region, the cache region including a cache and a third power line providing a second voltage to the cache, and arranged between the first core region and the second core region; and a first power connection line connecting the first power line to the second power line and arranged in the cache region.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: November 28, 2023
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Jisoo Hwang, Chunguan Kim, Heeseok Lee, Kyoungkuk Chae
  • Publication number: 20230214886
    Abstract: An operation method of an application system includes receiving a chat room-entry event notifying that a user enters the chat room from a terminal in which an application is installed, generating an entry trigger based on the chat room enter event, and providing user context suitable information inferred based on a user key included in the entry trigger to the chat room.
    Type: Application
    Filed: December 27, 2022
    Publication date: July 6, 2023
    Inventors: YOUNG JIN HUH, SUNG YONG CHANG, SOOK YOUNG LEE, JISOO HWANG, HYE RYEON LEE, SEON HWA KIM, YOUNGHAE LEE, JIN HWAN KIM
  • Publication number: 20220361339
    Abstract: A semiconductor package including a circuit board including a first wiring region, a die mounting region surrounding the first wiring region, and a second wiring region surrounding the die mounting region; a plurality of wiring balls on the first wiring region and the second wiring region and spaced apart from one another, the plurality of wiring balls including a plurality of first wiring balls on the first wiring region and a plurality of second wiring balls on the second wiring region; a die on the die mounting region, the die including a plurality of unit chips spaced apart from one another, and a die-through region corresponding to the first wiring region and exposing the first wiring balls; and a plurality of die balls on the die and the die mounting region, the plurality of die balls being spaced apart from one another and electrically coupled to the circuit board.
    Type: Application
    Filed: February 3, 2022
    Publication date: November 10, 2022
    Inventors: Junghwa KIM, Junso PAK, Heeseok LEE, Moonseob JEONG, Jisoo HWANG
  • Patent number: 11435226
    Abstract: Provided are an apparatus and method for measuring quantum efficiency of a detector using a single pulse laser. Quantum efficiency of the measurement target detector may be measured from 420 nm to 1600 nm having uncertainty of 2% to 4% (K=2) by comparing the reference detector and the measurement target detector significantly different in sensitivity using a single laser pulse as a spectral light source. Also, it is possible to directly compare the two detectors with a significant difference in sensitivity through a very simple setup that causes a portion of a laser pulse output from a light source part to be absorbed by the reference detector and the laser pulse reflected from the reference detector to be irradiated to the measurement target detector.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: September 6, 2022
    Assignee: Korea Research Institute of Standards and Science
    Inventors: Kee-Suk Hong, Dong-Hoon Lee, Seongchong Park, Jisoo Hwang
  • Publication number: 20220215034
    Abstract: An electronic apparatus is provided. The electronic apparatus includes a storage and a processor to generate first training data by performing transformation for first original data based on at least one first transform function input according to a user input, store first metadata including the at least one first transform function in the storage, generate second training data by performing transformation for second original data based on at least one first transform function included in the stored first metadata, generate third training data by performing transformation for the second training data based on at least one second transform function input according to a user input, and store second metadata including the at least one first transform function and the at least one second transform function in the storage.
    Type: Application
    Filed: October 6, 2021
    Publication date: July 7, 2022
    Inventors: Kangyong PARK, Seungho JUNG, Minhyeok KWEUN, Kyungjae KIM, Goeun KIM, Eunkyu OH, Hyun HEO, Jisoo HWANG
  • Publication number: 20220045004
    Abstract: A semiconductor chip includes a first core region including a first core and a first power line configured to provide a first voltage to the first core, a second core region including a second core and a second power line configured to provide the first voltage to the second core, a cache region between the first core region and the second core region, the cache region including a cache and a third power line providing a second voltage to the cache, and arranged between the first core region and the second core region; and a first power connection line connecting the first power line to the second power line and arranged in the cache region.
    Type: Application
    Filed: July 13, 2021
    Publication date: February 10, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jisoo HWANG, Chunguan KIM, Heeseok LEE, Kyoungkuk CHAE
  • Publication number: 20200381400
    Abstract: A semiconductor package may include a first substrate, a second substrate at least partially surrounding the first substrate, the first substrate disposed in an opening penetrating the second substrate, and a semiconductor chip on the first substrate. The first substrate may be spaced apart from the second substrate in the opening, and a thickness of the first substrate may be less than a thickness of the second substrate.
    Type: Application
    Filed: January 24, 2020
    Publication date: December 3, 2020
    Inventors: HEESEOK LEE, YUNHYEOK IM, JISOO HWANG
  • Publication number: 20190341734
    Abstract: Provided are an apparatus and method for measuring quantum efficiency of a detector using a single pulse laser. Quantum efficiency of the measurement target detector may be measured from 420 nm to 1600 nm having uncertainty of 2% to 4% (K=2) by comparing the reference detector and the measurement target detector significantly different in sensitivity using a single laser pulse as a spectral light source. Also, it is possible to directly compare the two detectors with a significant difference in sensitivity through a very simple setup that causes a portion of a laser pulse output from a light source part to be absorbed by the reference detector and the laser pulse reflected from the reference detector to be irradiated to the measurement target detector.
    Type: Application
    Filed: May 3, 2019
    Publication date: November 7, 2019
    Inventors: Kee-Suk HONG, Dong-Hoon LEE, Seongchong PARK, Jisoo HWANG
  • Patent number: 7701537
    Abstract: An optical diode. A cholesteric liquid crystal (CLC) layer has a selective reflection wavelength band with a left-handed helical structure, and a phase shifter for changing a phase difference between two intrinsic polarized light components of left-handed circularly polarized light having a wavelength within the selective reflection wavelength band of the CLC layer. When left-handed circularly polarized light having a wavelength within the selective reflection wavelength band of the CLC layer is incident on the phase shifter in the optical diode, the phase shifter turns the left-handed circularly polarized light into right-handed circularly polarized light, which can be transmitted through the CLC layer. When left-handed circularly polarized light having a wavelength within the selective reflection wavelength band of the CLC layer is incident on the CLC layer, it is selectively reflected by the CLC layer.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: April 20, 2010
    Assignees: Tokyo Institute of Technology, Nippon Oil Corporation
    Inventors: Hideo Takezoe, Byoungchoo Park, Myoung Hoon Song, Jisoo Hwang, Takehiro Toyooka, Suzushi Nishimura
  • Publication number: 20070221921
    Abstract: An optical diode which can lower the cost and save electric power is provided. An optical diode 21 of the present invention comprises a cholesteric liquid crystal (CLC) layer 2 having a selective reflection wavelength band with a left-handed helical structure, and a phase shifter 24 for changing the phase difference between two intrinsic polarized light components of left-handed circularly polarized light having a wavelength within the selective reflection wavelength band of the CLC layer 2. When left-handed circularly polarized light having a wavelength within the selective reflection wavelength band of the CLC layer 2 is incident on the phase shifter 24 in the optical diode 21, for example, the phase shifter 24 turns the left-handed circularly polarized light into right-handed circularly polarized light, this right-handed circularly polarized light can be transmitted through the CLC layer 2.
    Type: Application
    Filed: March 2, 2007
    Publication date: September 27, 2007
    Inventors: Hideo Takezoe, Byoungchoo Park, Myoung Song, Jisoo Hwang, Takehiro Toyooka, Suzushi Nishimura