Abstract: A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit substrate, a peripheral circuit element on the peripheral circuit substrate, and a wiring structure connected to the peripheral circuit element and a memory cell structure provided on the peripheral circuit structure. The memory cell structure includes a cell substrate including a cell array region, an extended region, and a through region, a mold structure including a plurality of gate electrodes sequentially provided on the cell array region and on the extended region in a step form, and a plurality of mold sacrifice films sequentially provided on the through region, a channel structure intersecting the plurality of gate electrodes on the cell array region, and a cell contact penetrating the mold structure on the extended region and configured to connect at least one of the plurality of gate electrodes and the wiring structure.

Abstract: A power voltage generator includes a voltage sensor and a power controller. The voltage sensor is configured to sense a first voltage in a first charge sharing period of a gate clock signal and a second voltage in a second charge sharing period of the gate clock signal. The power breaker is configured to disconnect a power based on the first voltage and the second voltage.

Abstract: A deposition apparatus includes an upper shower head and a lower shower head within a process chamber, the upper shower head and the lower shower head facing each other, a support structure between the upper shower head and the lower shower head, the support structure being connected to the lower shower head to support a wafer, and a plasma process region between the wafer supported by the support structure and the lower shower head, wherein the lower shower head includes lower holes to jet a lower gas in a direction of the wafer, wherein the upper shower head includes upper holes to jet an upper gas in a direction of the wafer, and wherein the support structure includes through opening portions to discharge a portion of the lower gas jetted through the lower holes to a space between the support structure and the upper shower head.

Abstract: A display device includes a display panel including a plurality of pixels, a controller which generates a gate reference signal, a gate control circuit which outputs a gate driving signal based on the gate reference signal, and a gate driving circuit which provides gate signals to the plurality of pixels based on the gate driving signal. The gate control circuit includes a protection enable circuit which detects a first period of the gate reference signal, determines whether the period of the gate reference signal is changed, and generates a protection enable signal when the first period of the gate reference signal is not changed, and an over-current protection circuit which generates an over-current occurrence signal by detecting an over-current of the gate driving signal, and stops outputting the gate driving signal based on the over-current occurrence signal and the protection enable signal.

Abstract: A power voltage generator includes a voltage sensor and a power controller. The voltage sensor is configured to sense a first voltage in a first charge sharing period of a gate clock signal and a second voltage in a second charge sharing period of the gate clock signal. The power breaker is configured to disconnect a power based on the first voltage and the second voltage.

Abstract: A method of fabricating a semiconductor device and a semiconductor processing apparatus are provided. The method of fabricating a semiconductor device comprises preparing a semiconductor substrate having a front side and a back side, opposing each other, and forming a material layer on the semiconductor substrate. The material layer is formed on at least a portion of the back side of the semiconductor substrate while being formed on the front side of the semiconductor substrate. The material layer formed on the at least a portion of the back side of the semiconductor substrate is removed, while the material layer formed on the front side of the semiconductor substrate remains. A semiconductor process is performed to fabricate the semiconductor device using the material layer remaining on the front side of the semiconductor substrate.

Abstract: A display device includes a display panel including a plurality of pixels, a controller which generates a gate reference signal, a gate control circuit which outputs a gate driving signal based on the gate reference signal, and a gate driving circuit which provides gate signals to the plurality of pixels based on the gate driving signal. The gate control circuit includes a protection enable circuit which detects a first period of the gate reference signal, determines whether the period of the gate reference signal is changed, and generates a protection enable signal when the first period of the gate reference signal is not changed, and an over-current protection circuit which generates an over-current occurrence signal by detecting an over-current of the gate driving signal, and stops outputting the gate driving signal based on the over-current occurrence signal and the protection enable signal.

Abstract: A deposition apparatus for depositing a material on a wafer, the apparatus including a lower shower head; an upper shower head disposed on the lower shower head, the upper shower head facing the lower shower head; and a support structure between the upper shower head and the lower shower head, the wafer being supportable by the support structure, wherein the upper shower head includes upper holes for providing an upper gas onto the wafer, the lower shower head includes lower holes for providing a lower gas onto the wafer, the support structure includes a ring body surrounding the wafer; a plurality of ring support shafts between the ring body and the lower shower head; and a plurality of wafer supports extending inwardly from a lower region of the ring body to support the wafer, and the plurality of wafer supports are spaced apart from one another.

Abstract: A method of fabricating a semiconductor device and a semiconductor processing apparatus are provided. The method of fabricating a semiconductor device comprises preparing a semiconductor substrate having a front side and a back side, opposing each other, and forming a material layer on the semiconductor substrate. The material layer is formed on at least a portion of the back side of the semiconductor substrate while being formed on the front side of the semiconductor substrate. The material layer formed on the at least a portion of the back side of the semiconductor substrate is removed, while the material layer formed on the front side of the semiconductor substrate remains. A semiconductor process is performed to fabricate the semiconductor device using the material layer remaining on the front side of the semiconductor substrate.

Abstract: A deposition apparatus includes an upper shower head and a lower shower head within a process chamber, the upper shower head and the lower shower head facing each other, a support structure between the upper shower head and the lower shower head, the support structure being connected to the lower shower head to support a wafer, and a plasma process region between the wafer supported by the support structure and the lower shower head, wherein the lower shower head includes lower holes to jet a lower gas in a direction of the wafer, wherein the upper shower head includes upper holes to jet an upper gas in a direction of the wafer, and wherein the support structure includes through opening portions to discharge a portion of the lower gas jetted through the lower holes to a space between the support structure and the upper shower head.

Abstract: A deposition apparatus for depositing a material on a wafer, the apparatus including a lower shower head; an upper shower head disposed on the lower shower head, the upper shower head facing the lower shower head; and a support structure between the upper shower head and the lower shower head, the wafer being supportable by the support structure, wherein the upper shower head includes upper holes for providing an upper gas onto the wafer, the lower shower head includes lower holes for providing a lower gas onto the wafer, the support structure includes a ring body surrounding the wafer; a plurality of ring support shafts between the ring body and the lower shower head; and a plurality of wafer supports extending inwardly from a lower region of the ring body to support the wafer, and the plurality of wafer supports are spaced apart from one another.

Abstract: A method of measuring a friction coefficient of a surface of a specimen includes: obtaining surface information of the specimen by using an atomic force microscope (AFM); calculating data of a friction coefficient of the surface of the specimen by using the surface information of the specimen; and mapping the data of the friction coefficient of the specimen to an image. The method of measuring a friction coefficient of a surface of a specimen may prevent a probe part of an atomic force microscope from being worn out and secure high reliability of the friction coefficient value by correcting the atomic force microscope using a specimen to be actually measured and measuring a fiction coefficient at the same time.

Abstract: A display apparatus including a display panel connected to a plurality of data lines, a data driver configured to generate a plurality of data voltages, and to apply the plurality of data voltages to the plurality of data lines, and a plurality of feedback lines disposed in a fan-out region between the display panel and the data driver, wherein the data driver is further configured to applies a first signal to each of the plurality of feedback lines, wherein delays by the fan-out region are obtained based on the first signal, the delays being associated with the plurality of data lines, and wherein the data driver is further configured to controls output times of the plurality of data voltages based on the delays.

Abstract: Provided is a surface treatment method, including: preparing a composite comprising chromium (Cr) of about 95 to 98 atomic percents and copper (Cu) of about 2 to 5 atomic percents with respect to the total number of atoms in the composite; and forming a coating layer comprising Cr of about 30 to 40 atomic, Cu of about 2 to 5 atomic percents, with respect to the total number of atoms of the coating layer, and N constituting the balance of the atoms of the coating layer, by sputtering from the composite in a nitrogen-containing atmospheric gas. Further, provided is a vehicle part, surface of which is treated with the same method.

Abstract: Provided is a surface treatment method, including: preparing a composite comprising chromium (Cr) of about 95 to 98 atomic percents and copper (Cu) of about 2 to 5 atomic percents with respect to the total number of atoms in the composite; and forming a coating layer comprising Cr of about 30 to 40 atomic, Cu of about 2 to 5 atomic percents, with respect to the total number of atoms of the coating layer, and N constituting the balance of the atoms of the coating layer, by sputtering from the composite in a nitrogen-containing atmospheric gas. Further, provided is a vehicle part, surface of which is treated with the same method.

Abstract: A method of measuring a friction coefficient of a surface of a specimen includes: obtaining surface information of the specimen by using an atomic force microscope (AFM); calculating data of a friction coefficient of the surface of the specimen by using the surface information of the specimen; and mapping the data of the friction coefficient of the specimen to an image. The method of measuring a friction coefficient of a surface of a specimen may prevent a probe part of an atomic force microscope from being worn out and secure high reliability of the friction coefficient value by correcting the atomic force microscope using a specimen to be actually measured and measuring a fiction coefficient at the same time.

Abstract: In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.

Abstract: A display apparatus including a display panel connected to a plurality of data lines, a data driver configured to generate a plurality of data voltages, and to apply the plurality of data voltages to the plurality of data lines, and a plurality of feedback lines disposed in a fan-out region between the display panel and the data driver, wherein the data driver is further configured to applies a first signal to each of the plurality of feedback lines, wherein delays by the fan-out region are obtained based on the first signal, the delays being associated with the plurality of data lines, and wherein the data driver is further configured to controls output times of the plurality of data voltages based on the delays.

Abstract: The present invention provides a method of producing D-type lactide from liquid D-type lactic acid, and a method for producing D-type polylactic acid having a weight average molecular weight of about 50,000˜20,000 g/mol from the produced D-type lactide. The method of the present invention is advantageous in that D-type lactide can be obtained at a high yield by a simple method, compared to the conventional production methods. Consequently, production cost of D-type polylactic acid that is finally obtained from D-type lactide can be reduced.

Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.