Patents by Inventor Ji-Yung LIN

Ji-Yung LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11012073
    Abstract: A circuit includes a level shifter circuit, an output circuit and a feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to receive at least an enable signal, a first input signal or a second input signal. The level shifter circuit is configured to generate at least a first signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, is configured to receive the first signal, and to generate at least an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit, the output circuit and the first voltage supply, and is configured to receive the enable signal, an inverted enable signal and the set of feedback signals.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Lun Ou, Jerry Chang Jui Kao, Lee-Chung Lu, Ruei-Wun Sun, Shang-Chih Hsieh, Ji-Yung Lin, Wei-Hsiang Ma, Yung-Chen Chien
  • Publication number: 20200350916
    Abstract: A circuit includes a level shifter circuit, an output circuit and a feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to receive at least an enable signal, a first input signal or a second input signal. The level shifter circuit is configured to generate at least a first signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, is configured to receive the first signal, and to generate at least an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit, the output circuit and the first voltage supply, and is configured to receive the enable signal, an inverted enable signal and the set of feedback signals.
    Type: Application
    Filed: July 22, 2020
    Publication date: November 5, 2020
    Inventors: Yu-Lun OU, Jerry Chang Jui KAO, Lee-Chung LU, Ruei-Wun SUN, Shang-Chih HSIEH, Ji-Yung LIN, Wei-Hsiang MA, Yung-Chen CHIEN
  • Patent number: 10735001
    Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit and a feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate a second input signal. The level shifter circuit is coupled to the input circuit, and configured to receive an enable signal, the first input signal or the second input signal, and to generate a first signal responsive to the enable signal or the first input signal. The output circuit is coupled to the level shifter circuit, and is configured to receive the first signal, and to generate an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit and output circuit, and is configured to receive the enable signal or the set of feedback signals.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Lun Ou, Jerry Chang Jui Kao, Lee-Chung Lu, Ruei-Wun Sun, Shang-Chih Hsieh, Ji-Yung Lin, Wei-Hsiang Ma, Yung-Chen Chien
  • Publication number: 20190319624
    Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit and a feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate a second input signal. The level shifter circuit is coupled to the input circuit, and configured to receive an enable signal, the first input signal or the second input signal, and to generate a first signal responsive to the enable signal or the first input signal. The output circuit is coupled to the level shifter circuit, and is configured to receive the first signal, and to generate an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit and output circuit, and is configured to receive the enable signal or the set of feedback signals.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 17, 2019
    Inventors: Yu-Lun OU, Jerry Chang Jui KAO, Lee-Chung LU, Ruei-Wun SUN, Shang-Chih HSIEH, Ji-Yung LIN, Wei-Hsiang MA, Yung-Chen CHIEN
  • Patent number: 10003342
    Abstract: A compressor circuit includes a plurality of inputs, a sum output, and a plurality of XOR circuits. Each XOR circuit of the plurality of XOR circuits includes first, second and third inputs, and a first output. The XOR circuit is configured to generate a logic value A?B?C at the first output, where A, B and C are logic values at the corresponding first, second and third inputs, and “?” is the XOR logic operation. The plurality of XOR circuits includes first and second XOR circuits. The first, second and third inputs of the first XOR circuit are coupled to corresponding inputs among the plurality of inputs of the compressor circuit. The first output of the first XOR circuit is coupled to the first input of the second XOR circuit. The first output of the second XOR circuit is coupled to the sum output.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: June 19, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lin Liu, Lee-Chung Lu, Meng-Hsueh Wang, Shang-Chih Hsieh, Henry Huang, Ji-Yung Lin
  • Publication number: 20160156358
    Abstract: A compressor circuit includes a plurality of inputs, a sum output, and a plurality of XOR circuits. Each XOR circuit of the plurality of XOR circuits includes first, second and third inputs, and a first output. The XOR circuit is configured to generate a logic value A?B?C at the first output, where A, B and C are logic values at the corresponding first, second and third inputs, and “?” is the XOR logic operation. The plurality of XOR circuits includes first and second XOR circuits. The first, second and third inputs of the first XOR circuit are coupled to corresponding inputs among the plurality of inputs of the compressor circuit. The first output of the first XOR circuit is coupled to the first input of the second XOR circuit. The first output of the second XOR circuit is coupled to the sum output.
    Type: Application
    Filed: June 16, 2015
    Publication date: June 2, 2016
    Inventors: Chi-Lin LIU, Lee-Chung LU, Meng-Hsueh WANG, Shang-Chih HSIEH, Henry HUANG, Ji-Yung LIN