Patents by Inventor Jia-Feng FANG

Jia-Feng FANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230403942
    Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.
    Type: Application
    Filed: August 28, 2023
    Publication date: December 14, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wei Liu, Jia-Feng Fang, Chun-Hsien Lin
  • Patent number: 11778917
    Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: October 3, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wei Liu, Jia-Feng Fang, Chun-Hsien Lin
  • Publication number: 20220013715
    Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.
    Type: Application
    Filed: August 4, 2020
    Publication date: January 13, 2022
    Inventors: Chia-Wei Liu, Jia-Feng Fang, Chun-Hsien Lin
  • Patent number: 10818556
    Abstract: A method for forming a semiconductor structure is provided. Multiple fins extending along a first direction are formed in a semiconductor substrate. The multiple fins includes a group of active fins, a pair of protection fins sandwiching about the group the active fins, and at least one dummy fin around the pair of protection fins. A fin cut process is performed to remove the at least one dummy fin around the pair of protection fins. After performing the fin cut process, trench isolation structures are formed within the trenches between the multiple fins. The trench isolation structures are subjected to an anneal process. After annealing the trench isolation structures, the pair of protection fins is removed.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 27, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hao-Yeh Liu, Jia-Feng Fang, Yu-Hsiang Lin, Ching-Hsiang Chiu, Chia-Wei Liu
  • Publication number: 20200194313
    Abstract: A method for forming a semiconductor structure is provided. Multiple fins extending along a first direction are formed in a semiconductor substrate. The multiple fins includes a group of active fins, a pair of protection fins sandwiching about the group the active fins, and at least one dummy fin around the pair of protection fins. A fin cut process is performed to remove the at least one dummy fin around the pair of protection fins. After performing the fin cut process, trench isolation structures are formed within the trenches between the multiple fins. The trench isolation structures are subjected to an anneal process. After annealing the trench isolation structures, the pair of protection fins is removed.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Hao-Yeh Liu, Jia-Feng Fang, Yu-Hsiang Lin, Ching-Hsiang Chiu, Chia-Wei Liu
  • Patent number: 9673053
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: June 6, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Rung-Yuan Lee, Yu-Ting Li, Jing-Yin Jhang, Chen-Yi Weng, Jia-Feng Fang, Yi-Wei Chen, Wei-Jen Wu, Po-Cheng Huang, Fu-Shou Tsai, Kun-Ju Li, Wen-Chin Lin, Chih-Chien Liu, Chih-Hsun Lin, Chun-Yuan Wu
  • Patent number: 9530871
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming an epitaxial layer on the fin-shaped structure; forming a first contact etch stop layer (CESL) on the epitaxial layer; forming a source/drain region in the epitaxial layer; and forming a second CESL on the first CESL.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: December 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Yueh Tsai, Jia-Feng Fang, Yi-Wei Chen, Jing-Yin Jhang, Rung-Yuan Lee, Chen-Yi Weng, Wei-Jen Wu
  • Patent number: 9443757
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming an epitaxial layer on the fin-shaped structure; forming a first contact etch stop layer (CESL) on the epitaxial layer; forming a source/drain region in the epitaxial layer; and forming a second CESL on the first CESL.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: September 13, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Yueh Tsai, Jia-Feng Fang, Yi-Wei Chen, Jing-Yin Jhang, Rung-Yuan Lee, Chen-Yi Weng, Wei-Jen Wu
  • Publication number: 20160148816
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 26, 2016
    Inventors: Rung-Yuan Lee, Yu-Ting Li, Jing-Yin Jhang, Chen-Yi Weng, Jia-Feng Fang, Yi-Wei Chen, Wei-Jen Wu, Po-Cheng Huang, Fu-Shou Tsai, Kun-Ju Li, Wen-Chin Lin, Chih-Chien Liu, Chih-Hsun Lin, Chun-Yuan Wu
  • Publication number: 20120167979
    Abstract: The present invention provides a thin film solar cell, which comprises: a substrate; a first electrode disposed on the substrate; a barrier layer disposed on the first electrode, wherein the material of the barrier layer is a conductive material; an ohmic contacting layer disposed on the barrier layer; an absorption layer disposed on the ohmic contacting layer; a buffer layer disposed on the absorption layer; a transparent conductive layer disposed on the buffer layer; and a second electrode disposed on the transparent conductive layer. In addition, the present invention also provides a method for manufacturing the aforementioned thin film solar cell.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 5, 2012
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Dung-Ching PERNG, Jia-Feng FANG