Patents by Inventor Jialei Liu
Jialei Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11958681Abstract: The present invention relates to a ventilating and blanking device for a coal storage Eurosilo. The ventilating and blanking device includes a top blanking pipe, an axial flow fan and a baffle door, the top blanking pipe including a first pipeline and a second pipeline, an air supply pipe is connected to a side wall of the second pipeline, and the baffle door is connected to a driving mechanism; during blanking, the driving mechanism drives the baffle door so as to make the baffle door close the air supply pipe and the axial flow fan is shut off; and during ventilation, the driving mechanism drives the baffle door so as to make the baffle door close the first pipeline, and the axial flow fan is turned on. Compared with the prior art, the present invention has the advantages of ventilation efficiency, good ventilation effect, etc.Type: GrantFiled: May 10, 2021Date of Patent: April 16, 2024Assignees: HUANENG POWER INTERNATIONAL, INC., SHANGHAI SHIDONGKOU FIRST POWER PLANTInventors: Zhong Ni, Zhiwei Sang, Zhongming Huang, Xin Hu, Pengxia Ni, Ping Zhu, Qinghan Zheng, Runhan Liu, Xiao Zhang, Jinxin Yu, Haifeng Guan, Jialei Deng
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Patent number: 11515400Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a substrate; forming a dummy gate structure including a dummy gate dielectric layer, an initial dummy gate electrode layer, and a first sidewall spacer; forming an isolation layer having a surface lower than or coplanar with the dummy gate structure; forming a dummy gate electrode layer having a surface lower than the isolation layer, and forming a first opening to expose a portion of the first sidewall spacer; forming a modified sidewall spacer from the exposed first sidewall spacer; forming a second opening by removing the dummy gate electrode layer; forming a third opening by removing the dummy gate dielectric layer and the modified sidewall spacer, where top of the third opening has a size larger than bottom of the third opening; and forming a gate structure in the third opening.Type: GrantFiled: September 1, 2020Date of Patent: November 29, 2022Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Ruizhi Tang, Jinyu Fu, Lin Liu, Bo Li, Peng Yang, Haojun Huang, Jialei Liu
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Publication number: 20210074829Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a substrate; forming a dummy gate structure including a dummy gate dielectric layer, an initial dummy gate electrode layer, and a first sidewall spacer; forming an isolation layer having a surface lower than or coplanar with the dummy gate structure; forming a dummy gate electrode layer having a surface lower than the isolation layer, and forming a first opening to expose a portion of the first sidewall spacer; forming a modified sidewall spacer from the exposed first sidewall spacer; forming a second opening by removing the dummy gate electrode layer; forming a third opening by removing the dummy gate dielectric layer and the modified sidewall spacer, where top of the third opening has a size larger than bottom of the third opening; and forming a gate structure in the third opening.Type: ApplicationFiled: September 1, 2020Publication date: March 11, 2021Inventors: Ruizhi TANG, Jinyu FU, Lin LIU, Bo LI, Peng YANG, Haojun HUANG, Jialei LIU
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Patent number: 9685382Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate including a PMOS region and an NMOS region. A spacer material layer is deposited. Then, a first photo masking and etch process is used to form first sidewall spacers on the sidewalls of the gate structures in the NMOS region. A sacrificial surface layer is formed. Next, a second photo masking and etch process is used to form second sidewall spacers on the sidewalls of the gate structures in the PMOS region. After the second photoresist layer is removed, with the sacrificial layer masking the NMOS region, stress layers are formed in source/drain regions in the PMOS region, and a cover layer is formed on the stress layers. The method further includes removing the sacrificial material layer, the first sidewall spacers, and the second sidewall spacer.Type: GrantFiled: July 28, 2016Date of Patent: June 20, 2017Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Jialei Liu
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Publication number: 20170170074Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate including a PMOS region and an NMOS region. A spacer material layer is deposited. Then, a first photo masking and etch process is used to form first sidewall spacers on the sidewalls of the gate structures in the NMOS region. A sacrificial surface layer is formed. Next, a second photo masking and etch process is used to form second sidewall spacers on the sidewalls of the gate structures in the PMOS region. After the second photoresist layer is removed, with the sacrificial layer masking the NMOS region, stress layers are formed in source/drain regions in the PMOS region, and a cover layer is formed on the stress layers. The method further includes removing the sacrificial material layer, the first sidewall spacers, and the second sidewall spacer.Type: ApplicationFiled: July 28, 2016Publication date: June 15, 2017Inventor: JIALEI LIU
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Patent number: 8936987Abstract: A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate; and forming gate structures on a surface of the semiconductor substrate. The method also includes forming sidewall spacers around the gate structures; and forming a protection layer on the sidewall spacers. Further, the method includes forming sigma shape trenches in the semiconductor substrate at sides of the gate structures; and forming SiGe structures with a surface protruding from the surface of the semiconductor substrate in the sigma shape trenches. Further, the method also includes removing the sidewall spacers and a portion of the protection layer; and forming lightly doped drain regions in the semiconductor substrate at both sides of the gate structures.Type: GrantFiled: January 23, 2014Date of Patent: January 20, 2015Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventor: Jialei Liu
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Publication number: 20140361339Abstract: A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate; and forming gate structures on a surface of the semiconductor substrate. The method also includes forming sidewall spacers around the gate structures; and forming a protection layer on the sidewall spacers. Further, the method includes forming sigma shape trenches in the semiconductor substrate at sides of the gate structures; and forming SiGe structures with a surface protruding from the surface of the semiconductor substrate in the sigma shape trenches. Further, the method also includes removing the sidewall spacers and a portion of the protection layer; and forming lightly doped drain regions in the semiconductor substrate at both sides of the gate structures.Type: ApplicationFiled: January 23, 2014Publication date: December 11, 2014Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventor: JIALEI LIU
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Patent number: 8372722Abstract: A method of fabricating semiconductor device includes forming a recess having a substantially rectangular section and forming an oxide layer on sidewalls and an oxide layer on a bottom of the recess by anisotropic oxidation, wherein the oxide layer on the sidewalls is thinner than the oxide layer on the bottom of recess. The method further includes completely removing the oxide layer on the sidewalls and partially removing the oxide layer on the bottom of the recess. The method also includes performing an orientation selective wet etching on the recess using a remaining oxide layer of the recess as a stop layer to shape the sidewalls into a ? shaped section. The method includes removing the remaining oxide layer using an isotropic wet etching.Type: GrantFiled: November 4, 2011Date of Patent: February 12, 2013Assignee: Semiconductor Manufacturing International (Beijing) CorporationInventors: Qingsong Wei, Yonggen He, Huanxin Liu, Jialei Liu, Chaowei Li
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Publication number: 20130017661Abstract: A method of fabricating semiconductor device includes forming a recess having a substantially rectangular section and forming an oxide layer on sidewalls and an oxide layer on a bottom of the recess by anisotropic oxidation, wherein the oxide layer on the sidewalls is thinner than the oxide layer on the bottom of recess. The method further includes completely removing the oxide layer on the sidewalls and partially removing the oxide layer on the bottom of the recess. The method also includes performing an orientation selective wet etching on the recess using a remaining oxide layer of the recess as a stop layer to shape the sidewalls into a ? shaped section. The method includes removing the remaining oxide layer using an isotropic wet etching.Type: ApplicationFiled: November 4, 2011Publication date: January 17, 2013Applicant: Semiconductor Manufacturing International (Beijing) CorporationInventors: QINGSONG WEI, YONGGEN He, HUANXIN Liu, Jialei Liu, Chaowei Li