Patents by Inventor Jiajie Cen
Jiajie Cen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240332075Abstract: Methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a first self-assembled monolayer (SAM) on the bottom of the gap; forming a barrier layer on the dielectric layer; selectively depositing a second self-assembled monolayer (SAM) on the barrier layer and on the bottom of the gap; treating the microelectronic device with a plasma to remove a first portion of the second self-assembled monolayer (SAM); selectively depositing a metal liner on the barrier layer on the sidewall; removing a second portion of the second self-assembled monolayer (SAM); and performing a gap fill process on the metal liner.Type: ApplicationFiled: March 22, 2024Publication date: October 3, 2024Applicant: Applied Materials, Inc.Inventors: Jiajie Cen, Kevin Kashefi, Zhiyuan Wu, Yang Zhou, Yong Jin Kim, Carmen Leal Cervantes, Ge Qu, Zheng Ju
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Publication number: 20240290655Abstract: A method of selectively filling a via with a simultaneous liner deposition in a semiconductor structure includes forming a passivation layer selectively on an exposed surface of a conductive layer within a via formed in a dielectric layer formed over the conductive layer, forming a barrier layer selectively on inner sidewalls of the via and a trench formed in the dielectric layer, selectively filling the via with a first conductive material at least partially and simultaneously depositing the first conductive material on the barrier layer on the inner sidewalls of the via and the trench, to form a liner on the inner sidewalls of the via and the trench, and filling the remaining of the via and the trench with a second conductive material.Type: ApplicationFiled: February 28, 2023Publication date: August 29, 2024Inventors: Zheng JU, Zhiyuan WU, Jiajie CEN, Feng Q. LIU, Feng CHEN
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Publication number: 20240258103Abstract: Embodiments of the disclosure relate to methods for forming electrical interconnects. Additional embodiments provide methods of forming and treating barrier and liner layers to improve film and material properties. In some embodiments, the resulting composite layers provide improved resistivity, decrease void formation and improve device reliability.Type: ApplicationFiled: January 25, 2024Publication date: August 1, 2024Applicant: Applied Materials, Inc.Inventors: Jiajie Cen, Ge Qu, Shinjae Hwang, Zheng Ju, Yang Zhou, Zhiyuan Wu, Feng Chen, Kevin Kashefi
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Publication number: 20240258164Abstract: Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A pre-clean process is performed before a self-assembled monolayer (SAM) is formed on the bottom of the gap. A barrier layer is selectively deposited on the sidewalls but not on the bottom of the gap. The SAM is removed after selectively depositing the barrier layer on the sidewalls.Type: ApplicationFiled: January 22, 2024Publication date: August 1, 2024Applicant: Applied Materials, Inc.Inventors: Jiajie Cen, Carmen Leal Cervantes, Yong Jin Kim, Kevin Kashefi, Xiaodong Wang
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Patent number: 12033846Abstract: One or more embodiments relates to a system and method for growing ultrasmooth and high quantum efficiency photocathodes. The method includes exposing a substrate of Si wafer to an alkali source; controlling co-evaporating growth and co-deposition forming a growth including Te; and monitoring a stoichiometry of the growth, forming the photocathodes.Type: GrantFiled: October 15, 2020Date of Patent: July 9, 2024Assignee: U.S. Department of EnergyInventors: Mengjia Gaowei, John Smedley, John Walsh, Jiajie Cen, John Jay Sinsheimer
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Publication number: 20240194605Abstract: A semiconductor structure includes a first level comprising a metal layer within a first dielectric layer formed on a substrate, a second level formed on the first level, the second level comprising an interconnect within a second dielectric layer and a barrier layer formed around the interconnect, and a metal capping layer disposed at an interface between the metal layer and the interconnect, wherein the metal capping layer comprises tungsten (W) and has a thickness of between 20 ? and 40 ?.Type: ApplicationFiled: December 8, 2023Publication date: June 13, 2024Inventors: Mohammad Mahdi TAVAKOLI, Avgerinos V. GELATOS, Jiajie CEN, Kevin KASHEFI, Joung Joo LEE, Zhihui LIU, Yang ZHOU, Zhiyuan WU, Meng-Shan WU
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Publication number: 20240186181Abstract: Methods to deposit a metal cap for an interconnect are disclosed. In embodiments, a method comprises contacting the substrate with an alkyl halide and a ruthenium metal precursor to form a metal cap for an interconnect.Type: ApplicationFiled: December 2, 2022Publication date: June 6, 2024Inventors: Ge QU, Qihao ZHU, Zheng JU, Yang ZHOU, Jiajie CEN, Feng Q. LIU, Zhiyuan WU, Feng CHEN, Kevin KASHEFI, Xianmin TANG, Jeffrey W. ANTHIS, Mark Joseph SALY
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Publication number: 20240153816Abstract: A method for forming a metal liner layer for an interconnect uses a multi-metal deposition process to produce a reduced thickness liner. The back-end-of-the-line packaging process may include forming a metal liner layer by depositing a ruthenium layer with a first thickness of approximately 5 angstroms or less and depositing a first cobalt layer with a second thickness of approximately 20 angstroms or less. In some embodiments, the ruthenium layer may be deposited on a previously formed barrier layer and then undergoes a treatment process before depositing the first cobalt layer. In some embodiments, the first cobalt layer may be deposited on the ruthenium layer or the ruthenium layer maybe deposited on the first cobalt layer. In some embodiments, the ruthenium layer is deposited on the first cobalt layer and a second cobalt layer is deposited on the ruthenium layer.Type: ApplicationFiled: November 4, 2022Publication date: May 9, 2024Inventors: Ge QU, Zhiyuan WU, Jiajie CEN, Feng CHEN
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Patent number: 11967525Abstract: Embodiments of the disclosure relate to methods of depositing tungsten. Some embodiments of the disclosure provide methods for depositing tungsten which are performed at relatively low temperatures. Some embodiments of the disclosure provide methods in which the ratio between reactant gasses is controlled. Some embodiments of the disclosure provide selective deposition of tungsten. Some embodiments of the disclosure provide methods for depositing tungsten films at a low temperature with relatively low roughness, stress and impurity levels.Type: GrantFiled: August 1, 2022Date of Patent: April 23, 2024Assignee: Applied Materials, Inc.Inventors: Yi Xu, Yufei Hu, Yu Lei, Kazuya Daito, Da He, Jiajie Cen
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Patent number: 11952655Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a physical vapor deposition processing chamber comprises a chamber body defining a processing volume, a substrate support disposed within the processing volume and comprising a substrate support surface configured to support a substrate, a power supply configured to energize a target for sputtering material toward the substrate, an electromagnet operably coupled to the chamber body and positioned to form electromagnetic filed lines through a sheath above the substrate during sputtering for directing sputtered material toward the substrate, and a controller operably coupled to the physical vapor deposition processing chamber for controlling the electromagnet based on a recipe comprising a pulsing schedule for pulsing the electromagnet during operation to control directionality of ions relative to a feature on the substrate.Type: GrantFiled: May 5, 2022Date of Patent: April 9, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Kevin Kashefi, Xiaodong Wang, Suhas Bangalore Umesh, Zheng Ju, Jiajie Cen
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Publication number: 20240038541Abstract: Methods for cleaning oxides from a substrate surface are performed without affecting low-k dielectric or carbon materials on the substrate. In some embodiments, the method may include performing a preclean process with a chlorine-based soak to remove oxides from a surface of a substrate in a back end of the line (BEOL) process and treating the surface of the substrate with a remote plasma with a hydrogen gas and at least one inert gas to remove residual chlorine residue from the surface of the substrate without damaging low-k dielectric material or carbon material on the substrate.Type: ApplicationFiled: October 6, 2022Publication date: February 1, 2024Inventors: Jiajie CEN, Xiaodong WANG, Kevin KASHEFI, Shi YOU
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Publication number: 20240006235Abstract: Described are methods for forming ruthenium doped niobium nitride barrier layers. The doped barrier layer provides improved adhesion at a thickness of less than about 15 ?.Type: ApplicationFiled: June 30, 2023Publication date: January 4, 2024Applicant: Applied Materials, Inc.Inventors: Jiajie Cen, Zheng Ju, Feng Chen, Jeffrey W. Antis, Bengamin Schmiege
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Publication number: 20230313364Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a physical vapor deposition processing chamber comprises a chamber body defining a processing volume, a substrate support disposed within the processing volume and comprising a substrate support surface configured to support a substrate, a power supply configured to energize a target for sputtering material toward the substrate, an electromagnet operably coupled to the chamber body and positioned to form electromagnetic filed lines through a sheath above the substrate during sputtering for directing sputtered material toward the substrate, and a controller operably coupled to the physical vapor deposition processing chamber for controlling the electromagnet based on a recipe comprising a pulsing schedule for pulsing the electromagnet during operation to control directionality of ions relative to a feature on the substrate.Type: ApplicationFiled: May 5, 2022Publication date: October 5, 2023Inventors: Kevin KASHEFI, Xiaodong Wang, Suhas Bangalore Umesh, Zheng Ju, Jiajie Cen
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Publication number: 20230098561Abstract: A method of gap filling a feature on a substrate decreases the feature-to-feature gap fill height variation by using a tungsten halide soak treatment. In some embodiments, the method may include heating a substrate to a temperature of approximately 350 degrees Celsius to approximately 450 degrees Celsius, exposing the substrate to a tungsten halide gas at a process pressure of approximately 5 Torr to approximately 25 Torr, soaking the substrate for a soak time of approximately 5 seconds to approximately 60 seconds with the tungsten halide gas, and performing a metal preclean process and a gap fill deposition on a plurality of features on the substrate after soaking of the substrate has completed.Type: ApplicationFiled: September 29, 2021Publication date: March 30, 2023Inventors: Jiajie CEN, Da HE, Yi XU, Yu LEI
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Publication number: 20220367264Abstract: Embodiments of the disclosure relate to methods of depositing tungsten. Some embodiments of the disclosure provide methods for depositing tungsten which are performed at relatively low temperatures. Some embodiments of the disclosure provide methods in which the ratio between reactant gasses is controlled. Some embodiments of the disclosure provide selective deposition of tungsten. Some embodiments of the disclosure provide methods for depositing tungsten films at a low temperature with relatively low roughness, stress and impurity levels.Type: ApplicationFiled: August 1, 2022Publication date: November 17, 2022Applicant: Applied Materials, Inc.Inventors: Yi Xu, Yufei Hu, Yu Lei, Kazuya Daito, Da He, Jiajie Cen
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Patent number: 11404313Abstract: Embodiments of the disclosure relate to methods of depositing tungsten. Some embodiments of the disclosure provide methods for depositing tungsten which are performed at relatively low temperatures. Some embodiments of the disclosure provide methods in which the ratio between reactant gasses is controlled. Some embodiments of the disclosure provide selective deposition of tungsten. Some embodiments of the disclosure provide methods for depositing tungsten films at a low temperature with relatively low roughness, stress and impurity levels.Type: GrantFiled: June 30, 2020Date of Patent: August 2, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Yi Xu, Yufei Hu, Yu Lei, Kazuya Daito, Da He, Jiajie Cen
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Publication number: 20210118640Abstract: One or more embodiments relates to a system and method for growing ultrasmooth and high quantum efficiency photocathodes. The method includes exposing a substrate of Si wafer to an alkali source; controlling co-evaporating growth and co-deposition forming a growth including Te; and monitoring a stoichiometry of the growth, forming the photocathodes.Type: ApplicationFiled: October 15, 2020Publication date: April 22, 2021Inventors: Mengjia Gaowei, John Smedley, John Walsh, Jiajie Cen, John Jay Sinsheimer
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Publication number: 20200335395Abstract: Embodiments of the disclosure relate to methods of depositing tungsten. Some embodiments of the disclosure provide methods for depositing tungsten which are performed at relatively low temperatures. Some embodiments of the disclosure provide methods in which the ratio between reactant gasses is controlled. Some embodiments of the disclosure provide selective deposition of tungsten. Some embodiments of the disclosure provide methods for depositing tungsten films at a low temperature with relatively low roughness, stress and impurity levels.Type: ApplicationFiled: June 30, 2020Publication date: October 22, 2020Applicant: Applied Materials, Inc.Inventors: Yi Xu, Yufei Hu, Yu Lei, Kazuya Daito, Da He, Jiajie Cen