Patents by Inventor Jian-Hong Lin

Jian-Hong Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180046044
    Abstract: An embedded touch panel and the manufacturing method thereof are disclosed. The embedded touch panel includes a TFT substrate, a liquid crystal layer, a color filter, a polarizer and a glass cover arranged in sequence, wherein the polarizer is a non-conductive polarizer. A transparent conductive layer is arranged between the polarizer and the color filter. The TFT substrate includes at least one grounded pin, and the transparent conductive layer electrically connects with the grounded pin on the TFT substrate. In view of the above, the transparent conductive layer and the non-conductive polarizer may replace the high impedance polarizer of the embedded touch panel so as to greatly reduce the manufacturing cost. In addition, by bonding the frame of the polarizer, the bubble issue occurring when bonding the polarizer may be avoided.
    Type: Application
    Filed: January 29, 2016
    Publication date: February 15, 2018
    Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventors: Yao-li HUANG, Gui CHEN, Jian-hong LIN
  • Patent number: 9875964
    Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bi-Ling Lin, Jian-Hong Lin, Ming-Hong Hsieh, Lee-Der Chen, Jiaw-Ren Shih, Chwei-Ching Chiu
  • Publication number: 20170338178
    Abstract: A method, for forming a semiconductor device structure, includes: forming a conductive structure over a substrate, wherein the conductive structure includes twin boundaries. The forming the conductive structure includes: manipulating process conditions so as to promote formation of the twin boundaries and yet control a density of the twin boundaries to be outside a range for which a portion of a curve is an asymptote of a constant value, the curve representing values of an atomic migration ratio corresponding to values of the density of the twin boundaries.
    Type: Application
    Filed: August 9, 2017
    Publication date: November 23, 2017
    Inventors: Jian-Hong LIN, Chwei-Ching CHIU, Yung-Huei LEE, Chien-Neng LIAO, Yu-Lun CHUEH, Tsung-Cheng CHAN, Chun-Lung HUANG
  • Patent number: 9817516
    Abstract: The present invention provides a Gate driver on Array circuit, a display panel and a display device. The Gate driver on Array circuit comprises: shift register SR circuits of multiple stages and a signal connection circuit of the shift register SR circuits of multiple stages, and the shift register SR circuit of each stage comprises: a pre-charge controller, three thin film transistors and a capacitor; and the SR circuit of each stage further comprises: at least one switch, and a G electrode of the switch is inputted with a touch panel scan signal, and a S electrode of the switch is coupled to a K output end, and a D electrode of the switch is coupled to a scan line gate electrode signal of the SR circuit; the K output end inputs a K signal, and the K signal is synchronized with a touch panel signal TP signal.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: November 14, 2017
    Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd, Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventors: Jian-Hong Lin, Yucheng Tsai, Yaoli Huang
  • Patent number: 9778526
    Abstract: A pixel array includes pixel rows. Each pixel row includes a first gate line, a second gate line, sub-pixels and data lines. Each data line includes a main portion, a branch portion and a connecting portion. The main portions of the data lines are arranged along a second direction in sequence. The branch portions and the main portions of the data lines are arranged alternately along the second direction in sequence, and each sub-pixel is disposed between any two of the adjoining main portion and branch portion. The connecting portion of each of the data lines is disposed between the first gate line and the second gate line, the connecting portion of each data line is electrically connected with the main portion and the branch portion of each data line, and the connecting portion of each data line penetrates through the corresponding sub-pixel along the second direction.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 3, 2017
    Assignee: AU OPTRONICS CORP.
    Inventors: Shiuan-Hua Huang, Jian-Hong Lin
  • Patent number: 9778773
    Abstract: The disclosure provides a method and a device for decreasing a leakage current of an in-cell touch liquid crystal panel. The method includes: outputting a signal after adjusting a voltage by the data line during a time period of scanning a touch signal according to a voltage on the data line connected to the pixel and a signal inputted to a common electrode of the pixel for scanning the touch signal, so as to decrease a drain source voltage of a thin film transistor in the pixel. According the method and the device, it is capable of decreasing the leakage current of the in-cell touch liquid crystal panel effectively.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 3, 2017
    Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd, Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventors: Jian-hong Lin, Yucheng Tsai, Yao-li Huang
  • Patent number: 9761523
    Abstract: A semiconductor device structure with twin-boundaries and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive structure formed over the substrate. The conductive structure includes twin boundaries, and a density of the twin boundaries is in a range from about 25 ?m?1 to about 250 ?m?1.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong Lin, Chwei-Ching Chiu, Yung-Huei Lee, Chien-Neng Liao, Yu-Lun Chueh, Tsung-Cheng Chan, Chun-Lung Huang
  • Publication number: 20170249036
    Abstract: The disclosure provides a method and a device for decreasing a leakage current of an in-cell touch liquid crystal panel. The method includes: outputting a signal after adjusting a voltage by the data line during a time period of scanning a touch signal according to a voltage on the data line connected to the pixel and a signal inputted to a common electrode of the pixel for scanning the touch signal, so as to decrease a drain source voltage of a thin film transistor in the pixel. According the method and the device, it is capable of decreasing the leakage current of the in-cell touch liquid crystal panel effectively.
    Type: Application
    Filed: October 30, 2015
    Publication date: August 31, 2017
    Inventors: Jian-hong LIN, Yucheng TSAI, Yao-li HUANG
  • Publication number: 20170242513
    Abstract: The present invention provides a touch panel wire arrangement circuit, the touch panel wire arrangement circuit comprises: an ITO region, metal wires, a touch control hole and an integrated circuit; the touch panel wire arrangement circuit further comprises: a rear end switch set, and the rear end switch set comprises: a plurality of switches, and a G electrode of each switch in the plurality of switches is inputted with a switch signal, and D electrodes of the plurality of switches are sequentially coupled to rear ends of the metal wires, and S electrodes of the plurality of switches are inputted with at least one voltage signals; the switch signal is: a signal at high voltage level as a touch panel TP signal does not function; the voltage signal is a common voltage V-com signal as the touch panel is in a display state.
    Type: Application
    Filed: October 28, 2015
    Publication date: August 24, 2017
    Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd., WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: JIAN-HONG LIN
  • Publication number: 20170235421
    Abstract: The present invention provides a Gate driver on Array circuit, a display panel and a display device. The Gate driver on Array circuit comprises: shift register SR circuits of multiple stages and a signal connection circuit of the shift register SR circuits of multiple stages, and the shift register SR circuit of each stage comprises: a pre-charge controller, three thin film transistors and a capacitor; and the SR circuit of each stage further comprises: at least one switch, and a G electrode of the switch is inputted with a touch panel scan signal, and a S electrode of the switch is coupled to a K output end, and a D electrode of the switch is coupled to a scan line gate electrode signal of the SR circuit; the K output end inputs a K signal, and the K signal is synchronized with a touch panel signal TP signal.
    Type: Application
    Filed: October 28, 2015
    Publication date: August 17, 2017
    Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd., WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventors: JIAN-HONG LIN, Yucheng TSAI, Yaoli HUANG
  • Patent number: 9734271
    Abstract: In some embodiments, in a method for a semiconductor device having an interconnect structure, a design layout is received. A metal line in the design layout is identified, which has at least one via thereon and does not couple downward with an oxide diffusion region. The area of a gate oxide coupled with the metal line is obtained from the design layout. The method comprises determining whether the area of the gate oxide is greater than a first predetermined value. When the area of the gate oxide is greater than the first predetermined value, a charge release path is coupled with the metal line.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: August 15, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu Ching Lee, Jian-Hong Lin, Te-Liang Lee, Jyh-Weei Hsia
  • Publication number: 20170169152
    Abstract: In some embodiments, in a method for a semiconductor device having an interconnect structure, a design layout is received. A metal line in the design layout is identified, which has at least one via thereon and does not couple downward with an oxide diffusion region. The area of a gate oxide coupled with the metal line is obtained from the design layout. The method comprises determining whether the area of the gate oxide is greater than a first predetermined value. When the area of the gate oxide is greater than the first predetermined value, a charge release path is coupled with the metal line.
    Type: Application
    Filed: December 10, 2015
    Publication date: June 15, 2017
    Inventors: YU CHING LEE, JIAN-HONG LIN, TE-LIANG LEE, JYH-WEEI HSIA
  • Patent number: 9601373
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes the following operations: (i) forming a transistor having a source, a drain and a gate on a semiconductor substrate; (ii) forming a conductive contact located on and in contact with at least one of the source and the drain; and (iii) forming a capacitor having a first electrode and a second electrode on the semiconductor substrate, in which at least one of the first and second electrodes is formed using front-end-of line (FEOL) processes or middle-end-of line (MEOL) processes.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Shan Wang, Jian-Hong Lin, Shun-Yi Lee
  • Publication number: 20170053865
    Abstract: A semiconductor device structure with twin-boundaries and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive structure formed over the substrate. The conductive structure includes twin boundaries, and a density of the twin boundaries is in a range from about 25 ?m?1 to about 250 ?m?1.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 23, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Jian-Hong LIN, Chwei-Ching CHIU, Yung-Huei LEE, Chien-Neng LIAO, Yu-Lun CHUEH, Tsung-Cheng CHAN, Chun-Lung HUANG
  • Publication number: 20160370636
    Abstract: A pixel array includes pixel rows. Each pixel row includes a first gate line, a second gate line, sub-pixels and data lines. Each data line includes a main portion, a branch portion and a connecting portion. The main portions of the data lines are arranged along a second direction in sequence. The branch portions and the main portions of the data lines are arranged alternately along the second direction in sequence, and each sub-pixel is disposed between any two of the adjoining main portion and branch portion. The connecting portion of each of the data lines is disposed between the first gate line and the second gate line, the connecting portion of each data line is electrically connected with the main portion and the branch portion of each data line, and the connecting portion of each data line penetrates through the corresponding sub-pixel along the second direction.
    Type: Application
    Filed: February 19, 2016
    Publication date: December 22, 2016
    Inventors: Shiuan-Hua Huang, Jian-Hong Lin
  • Publication number: 20160372368
    Abstract: A method of making a semiconductor device includes forming a first opening in an insulating layer, forming a second opening in the insulating layer, forming a third opening in the insulating layer and filling the first opening, the second opening and the third opening with a conductive material. The first opening has a width and a length. The second opening has a width less than the length of the first opening, and is electrically connected to the first opening. The third opening has a width less than the width of the second opening, and is electrically connected to the second opening.
    Type: Application
    Filed: September 2, 2016
    Publication date: December 22, 2016
    Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Shiou-Fan CHEN, Chwei-Ching CHIU, Yung-Huei LEE
  • Patent number: 9449919
    Abstract: A semiconductor device includes a first interconnect structure. The first interconnect structure includes a first interconnect portion, a second interconnect portion and a third interconnect portion. The first interconnect portion has a width and a length. The second interconnect portion has a width less than the length of the first interconnect portion. The second interconnect portion is connected to the first interconnect portion. The third interconnect portion has a width less than the width of the second interconnect portion. The third interconnect portion is connected to the second interconnect portion.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong Lin, Hsin-Chun Chang, Shiou-Fan Chen, Chwei-Ching Chiu, Yung-Huei Lee
  • Publication number: 20160247721
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes the following operations: (i) forming a transistor having a source, a drain and a gate on a semiconductor substrate; (ii) forming a conductive contact located on and in contact with at least one of the source and the drain; and (iii) forming a capacitor having a first electrode and a second electrode on the semiconductor substrate, in which at least one of the first and second electrodes is formed using front-end-of line (FEOL) processes or middle-end-of line (MEOL) processes.
    Type: Application
    Filed: May 3, 2016
    Publication date: August 25, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Shan WANG, Jian-Hong LIN, Shun-Yi LEE
  • Patent number: 9425330
    Abstract: A capacitor includes a first electrode including a plurality of first conductive lines, at least one first via, and at least one second via. The first conductive lines are parallel and connected to a first periphery conductive line. The first conductor lines in adjacent layers are coupled by the at least one first and second via. The at least one first via has a first length, and the at least one second via has a second length. The capacitor includes a second electrode opposite to the first electrode. The second electrode includes a plurality of second conductive lines and at least one third via. The second conductive lines are parallel and connected to a second periphery conductive line. The second conductor lines in adjacent layers are coupled by the at least one third via. The capacitor includes at least one oxide layer between the first electrode and the second electrode.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: August 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Shan Wang, Jian-Hong Lin, Chien-Jung Wang
  • Publication number: 20160240472
    Abstract: A semiconductor device includes a first interconnect structure. The first interconnect structure includes a first interconnect portion, a second interconnect portion and a third interconnect portion. The first interconnect portion has a width and a length. The second interconnect portion has a width less than the length of the first interconnect portion. The second interconnect portion is connected to the first interconnect portion. The third interconnect portion has a width less than the width of the second interconnect portion. The third interconnect portion is connected to the second interconnect portion.
    Type: Application
    Filed: February 12, 2015
    Publication date: August 18, 2016
    Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Shiou-Fan CHEN, Chwei-Ching CHIU, Yung-Huei LEE