Patents by Inventor Jian-Hong Lin

Jian-Hong Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140347586
    Abstract: A liquid crystal display device includes a first substrate, a second substrate, and a plurality of spacers. The first substrate includes a plurality of pixel units, which include at least two gate lines, and two neighboring thin film transistors connected to two gate lines, respectively. The second substrate is opposed to the first substrate. At least one of the spacers overlaps with at least a part of the first thin film transistor and at least a part of the second thin film transistor in a top view.
    Type: Application
    Filed: August 20, 2013
    Publication date: November 27, 2014
    Applicant: AU OPTRONICS CORP.
    Inventors: Chun-Min WANG, Chung-Min SHEN, Jian-Hong LIN
  • Patent number: 8848374
    Abstract: A semiconductor structure for dissipating heat away from a resistor having neighboring devices and interconnects. The semiconductor structure includes a semiconductor substrate, a resistor disposed above the semiconductor substrate, and a thermal protection structure disposed above the resistor. The thermal protection structure has a plurality of heat dissipating elements, the heat dissipating elements having one end disposed in thermal conductive contact with the thermal protection structure and the other end in thermal conductive contact with the semiconductor substrate. The thermal protection structure receives the heat generated from the resistor and the heat dissipating elements dissipates the heat to the semiconductor substrate.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Hong Lin, Chin Chuan Peng, Tzu-Li Lee, Bi-Ling Lin, Bor-Jou Wei, Chien Shih Tsai
  • Patent number: 8755000
    Abstract: A display panel including a first substrate, a second substrate, and a liquid crystal layer. The first substrate comprises a display region and a peripheral circuit region adjacent to the display region, and the first substrate includes a pixel array, a plurality of test shorting bars, and a plurality of wires. The pixel array is disposed in the display region. The test shorting bars are disposed in the peripheral circuit region. The wires are disposed in the peripheral circuit region and electrically connected with the pixel array. Moreover, at least one wire and one of the test shorting bars respectively share a part for connecting with each other and forming a common trace. Additionally, the second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: June 17, 2014
    Assignee: Au Optronics Corporation
    Inventor: Jian-Hong Lin
  • Publication number: 20140145194
    Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 29, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bi-Ling Lin, Jian-Hong Lin, Ming-Hong Hsieh, Lee-Der Chen, Jiaw-Ren Shih, Chwei-Ching Chiu
  • Patent number: 8729705
    Abstract: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: May 20, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Jung Wang, Jian-Hong Lin
  • Publication number: 20140103496
    Abstract: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.
    Type: Application
    Filed: December 18, 2013
    Publication date: April 17, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Jung Wang, Jian-Hong Lin
  • Patent number: 8674508
    Abstract: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Jung Wang, Jian-Hong Lin
  • Patent number: 8670102
    Abstract: A display panel includes an active device array substrate, an opposite substrate, and a liquid crystal layer. The active device array substrate includes a substrate and further includes a pixel array, signal lines, and first and second repairing lines all disposed on the substrate. The signal lines electrically connect the pixel array. The first repairing line includes first and second line segments respectively located on first and second sides of the pixel array. The first side is substantially perpendicular to the second side. The first and second line segments are electrically connected. The second repairing line includes third and fourth line segments respectively located on third and second sides of the pixel array. The third side is substantially parallel to the first side. The fourth and third line segments are electrically connected. The opposite substrate above the active device array substrate does not cover the first and third line segments.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: March 11, 2014
    Assignee: Au Optronics Corporation
    Inventors: Mien-Mien Cheng, Yi-Suei Liao, Jian-Hong Lin, Chien-Feng Chiu
  • Patent number: 8648592
    Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: February 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bi-Ling Lin, Jian-Hong Lin, Ming-Hong Hsieh, Lee-Der Chen, Jiaw-Ren Shih, Chwei-Ching Chiu
  • Patent number: 8541264
    Abstract: A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: September 24, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hong Lin, Kang-Cheng Lin, Tzu-Li Lee
  • Patent number: 8508503
    Abstract: A touch panel includes a touch sensor, a liquid crystal panel, and a reverse circuit. The reverse circuit receives common voltage ripples of the liquid crystal panel, and outputs reversed common voltage ripples after reversing the common voltage ripples. After the touch sensor receives the reversed common voltage ripples, the touch sensor outputs a sensing signal according to the reversed common voltage ripples.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: August 13, 2013
    Assignee: AU Optronics Corp.
    Inventors: Jian-Hong Lin, Wen-Rei Guo, Ching-Hua Chuang
  • Publication number: 20130127016
    Abstract: A capacitor includes a first electrode including a plurality of first conductive lines, at least one first via, and at least one second via. The first conductive lines are parallel and connected to a first periphery conductive line. The first conductor lines in adjacent layers are coupled by the at least one first and second via. The at least one first via has a first length, and the at least one second via has a second length. The capacitor includes a second electrode opposite to the first electrode. The second electrode includes a plurality of second conductive lines and at least one third via. The second conductive lines are parallel and connected to a second periphery conductive line. The second conductor lines in adjacent layers are coupled by the at least one third via. The capacitor includes at least one oxide layer between the first electrode and the second electrode.
    Type: Application
    Filed: January 18, 2013
    Publication date: May 23, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Shan WANG, Jian-Hong LIN, Chien-Jung WANG
  • Publication number: 20130063175
    Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.
    Type: Application
    Filed: September 13, 2011
    Publication date: March 14, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bi-Ling Lin, Jian-Hong Lin, Ming-Hong Hsieh, Lee-Der Chen, Jiaw-Ren Shih, Chwei-Ching Chiu
  • Patent number: 8379365
    Abstract: A capacitor includes the first electrode including the first conductive lines and vias. The first conductive lines on the same layer are parallel to each other and connected to a first periphery conductive line. The first conductor lines are aligned in adjacent layers and are coupled to each other by the vias. The capacitor further includes a second electrode aligned opposite to the first electrode including second conductive lines and vias. The second conductive lines on the same layer are parallel to each other and connected to a second periphery conductive line. The second conductor lines are aligned in adjacent layers and are coupled to each other by the vias. The capacitor further includes oxide layers formed between the first electrode and the second electrode. The vias have rectangular (slot) shapes on a layout. In one embodiment, the conductive lines and vias are metal, e.g. copper, aluminum, or tungsten.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: February 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Shan Wang, Jian-Hong Lin, Chien-Jung Wang
  • Publication number: 20120276732
    Abstract: A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.
    Type: Application
    Filed: July 12, 2012
    Publication date: November 1, 2012
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Jian-Hong Lin, Kang-Cheng Lin, Tzu-Li Lee
  • Publication number: 20120268434
    Abstract: A display panel including a first substrate, a second substrate, and a liquid crystal layer. The first substrate comprises a display region and a peripheral circuit region adjacent to the display region, and the first substrate includes a pixel array, a plurality of test shorting bars, and a plurality of wires. The pixel array is disposed in the display region. The test shorting bars are disposed in the peripheral circuit region. The wires are disposed in the peripheral circuit region and electrically connected with the pixel array. Moreover, at least one wire and one of the test shorting bars respectively share a part for connecting with each other and forming a common trace. Additionally, the second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate.
    Type: Application
    Filed: May 14, 2012
    Publication date: October 25, 2012
    Applicant: AU OPTRONICS CORPORATION
    Inventor: Jian-Hong Lin
  • Publication number: 20120205206
    Abstract: A hydraulic buffer device includes a first chamber, a second chamber, and a buffering space disposed under the first and second chambers, an air bladder disposed in the buffering space, an oil chamber disposed above the first and second chambers and divided by a piston into upper and lower chamber portions, and an annular passage disposed around the oil chamber. When the piston is moved downwardly within the oil chamber, the hydraulic oil flows from the lower chamber portion into the buffering space via the first chamber to contract the air bladder so that, upon expansion of the air bladder, air pressure in the air bladder pushes the hydraulic oil to flow from the buffering space into the upper chamber portion via the second chamber and the annular passage.
    Type: Application
    Filed: January 3, 2012
    Publication date: August 16, 2012
    Applicant: TEH LIN PROSTHETIC & ORTHOPAEDIC INC.
    Inventors: Jian-Yu Chen, Ming-Liang Wong, Chih-Ming Yu, Wun-Ya Gao, Jian-Hong Lin
  • Publication number: 20120209406
    Abstract: A foot plate device is connected to a prosthetic lower leg of an artificial foot, and includes a flexible foot plate. The foot plate has a front plate section, an inclined intermediate plate section extending rearwardly and upwardly from a rear end of the front plate section, and a rear plate section extending rearwardly from a rear end of the intermediate plate section and generally parallel to the front plate section. The front plate section has at least one open-ended slot formed vertically therethrough and extending across the front plate section along a longitudinal direction of the foot plate, so as to divide the front plate section into two force-receiving plate portions. The rear plate section is connected with the prosthetic lower leg.
    Type: Application
    Filed: February 14, 2012
    Publication date: August 16, 2012
    Applicant: TEH LIN PROSTHETIC & ORTHOPAEDIC INC.
    Inventors: Jian-Yu Chen, Chia-Chung WU, Wun-Ya Gao, Jian-Hong Lin
  • Patent number: 8242576
    Abstract: A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: August 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hong Lin, Kang-Cheng Lin, Tzu-Li Lee
  • Patent number: 8212330
    Abstract: An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: July 3, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jian-Hong Lin, Tzu-Li Lee