Patents by Inventor Jian-Hong Lin

Jian-Hong Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120205206
    Abstract: A hydraulic buffer device includes a first chamber, a second chamber, and a buffering space disposed under the first and second chambers, an air bladder disposed in the buffering space, an oil chamber disposed above the first and second chambers and divided by a piston into upper and lower chamber portions, and an annular passage disposed around the oil chamber. When the piston is moved downwardly within the oil chamber, the hydraulic oil flows from the lower chamber portion into the buffering space via the first chamber to contract the air bladder so that, upon expansion of the air bladder, air pressure in the air bladder pushes the hydraulic oil to flow from the buffering space into the upper chamber portion via the second chamber and the annular passage.
    Type: Application
    Filed: January 3, 2012
    Publication date: August 16, 2012
    Applicant: TEH LIN PROSTHETIC & ORTHOPAEDIC INC.
    Inventors: Jian-Yu Chen, Ming-Liang Wong, Chih-Ming Yu, Wun-Ya Gao, Jian-Hong Lin
  • Patent number: 8242576
    Abstract: A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: August 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hong Lin, Kang-Cheng Lin, Tzu-Li Lee
  • Patent number: 8212330
    Abstract: An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: July 3, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jian-Hong Lin, Tzu-Li Lee
  • Patent number: 8208084
    Abstract: An array substrate having a display region and a peripheral circuit region adjacent to the display region is provided. The array substrate includes a pixel array, a plurality of test shorting bars and a plurality of wires. The pixel array is disposed in the display region. The test shorting bars are disposed in the peripheral circuit region. The wires electrically connected with the pixel array are disposed in the peripheral circuit region. Specially, at least one wire and the test shorting bar share a part for connecting each other and the part forms a common trace.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: June 26, 2012
    Assignee: Au Optronics Corporation
    Inventor: Jian-Hong Lin
  • Publication number: 20120146920
    Abstract: A touch panel includes a touch sensor, a liquid crystal panel, and a reverse circuit. The reverse circuit receives common voltage ripples of the liquid crystal panel, and outputs reversed common voltage ripples after reversing the common voltage ripples. After the touch sensor receives the reversed common voltage ripples, the touch sensor outputs a sensing signal according to the reversed common voltage ripples.
    Type: Application
    Filed: March 28, 2011
    Publication date: June 14, 2012
    Inventors: Jian-Hong Lin, Wen-Rei Guo, Ching-Hua Chuang
  • Publication number: 20120050658
    Abstract: A display panel includes an active device array substrate, an opposite substrate, and a liquid crystal layer. The active device array substrate includes a substrate and further includes a pixel array, signal lines, and first and second repairing lines all disposed on the substrate. The signal lines electrically connect the pixel array. The first repairing line includes first and second line segments respectively located on first and second sides of the pixel array. The first side is substantially perpendicular to the second side. The first and second line segments are electrically connected. The second repairing line includes third and fourth line segments respectively located on third and second sides of the pixel array. The third side is substantially parallel to the first side. The fourth and third line segments are electrically connected. The opposite substrate above the active device array substrate does not cover the first and third line segments.
    Type: Application
    Filed: January 13, 2011
    Publication date: March 1, 2012
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Mien-Mien Cheng, Yi-Suei Liao, Jian-Hong Lin, Chien-Feng Chiu
  • Publication number: 20120002375
    Abstract: A semiconductor structure for dissipating heat away from a resistor having neighboring devices and interconnects. The semiconductor structure includes a semiconductor substrate, a resistor disposed above the semiconductor substrate, and a thermal protection structure disposed above the resistor. The thermal protection structure has a plurality of heat dissipating elements, the heat dissipating elements having one end disposed in thermal conductive contact with the thermal protection structure and the other end in thermal conductive contact with the semiconductor substrate. The thermal protection structure receives the heat generated from the resistor and the heat dissipating elements dissipates the heat to the semiconductor substrate.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 5, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong LIN, Chin Chuan PENG, Tzu-Li LEE, Bi-Ling LIN, Bor-Jou WEI, Chien Shih TSAI
  • Patent number: 8068577
    Abstract: The present invention relates to a pull-down control circuit and a shift register of using same. In one embodiment, the pull-down control circuit includes a release circuit and four transistors T4, T5, T6 and T7 electrically coupled to each other. The release circuit is adapted for causing the transistor T5 to be turned on and off alternately, thereby substantially reducing the stress thereon, improving the reliability and prolonging the lifetime of the shift register.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: November 29, 2011
    Assignee: AU Optronics Corporation
    Inventors: Yi-Suei Liao, Jian-Hong Lin
  • Publication number: 20110108945
    Abstract: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.
    Type: Application
    Filed: January 17, 2011
    Publication date: May 12, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Jung Wang, Jian-Hong Lin
  • Publication number: 20110069806
    Abstract: The present invention relates to a pull-down control circuit and a shift register of using same. In one embodiment, the pull-down control circuit includes a release circuit and four transistors T4, T5, T6 and T7 electrically coupled to each other. The release circuit is adapted for causing the transistor T5 to be turned on and off alternately, thereby substantially reducing the stress thereon, improving the reliability and prolonging the lifetime of the shift register.
    Type: Application
    Filed: September 23, 2009
    Publication date: March 24, 2011
    Applicant: AU Optronics
    Inventors: Yi-Suei Liao, Jian-Hong Lin
  • Patent number: 7893459
    Abstract: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: February 22, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Jung Wang, Jian-Hong Lin
  • Publication number: 20110025590
    Abstract: A display device having bi-directional scan mechanism includes a plurality of gate lines, a first shift register circuit and a second shift register circuit. The first shift register circuit includes a plurality of forward shift register stages. The second shift register circuit includes a plurality of backward shift register stages. Each of the gate lines is electrically connected to both a corresponding forward shift register stage and a corresponding backward shift register stage. When the first shift register circuit is enabled, the forward shift register stages are employed to provide plural forward gate signals sequentially enabled for scanning the gate lines based on a first sequence. When the second shift register circuit is enabled, the backward shift register stages are employed to provide plural backward gate signals sequentially enabled for scanning the gate lines based on a second sequence opposite to the first sequence.
    Type: Application
    Filed: December 4, 2009
    Publication date: February 3, 2011
    Inventors: Jian-Hong Lin, Wei-Cheng Lin
  • Publication number: 20100327456
    Abstract: An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.
    Type: Application
    Filed: September 10, 2010
    Publication date: December 30, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jian-Hong Lin, Tzu-Li Lee
  • Publication number: 20100271753
    Abstract: A capacitor includes the first electrode comprising the first conductive lines and vias, where the first conductive lines on the same layer are parallel to each other and connected to the first periphery conductive line, and the first conductor lines aligned in adjacent layers are coupled to each other by the vias; the second electrode aligned opposite to the first electrode comprising the second conductive lines and vias, where the second conductive lines on the same layer are parallel to each other and connected to the second periphery conductive line, and the second conductor lines aligned in adjacent layers are coupled to each other by the vias; and oxide layers formed between the first electrode and the second electrode, where the vias have rectangular (slot) shape on a layout. In one embodiment, the conductive lines and vias are metal, e.g. copper, aluminum, or tungsten. The vias can have various sizes.
    Type: Application
    Filed: April 27, 2010
    Publication date: October 28, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Shan WANG, Jian-Hong LIN, Chien-Jung WANG
  • Patent number: 7816256
    Abstract: An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: October 19, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jian-Hong Lin, Tzu-Li Lee
  • Patent number: 7667289
    Abstract: A laser fuse structure for a semiconductor device, the laser fuse structure having an array of laser fuses wherein one or more of the fuses in the array have a tortuous fuse line extending between first and second connectors that connect the fuse to an underlying circuit area.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: February 23, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hong Lin, Kang-Cheng Lin
  • Publication number: 20100014030
    Abstract: An array substrate having a display region and a peripheral circuit region adjacent to the display region is provided. The array substrate includes a pixel array, a plurality of test shorting bars and a plurality of wires. The pixel array is disposed in the display region. The test shorting bars are disposed in the peripheral circuit region. The wires electrically connected with the pixel array are disposed in the peripheral circuit region. Specially, at least one wire and the test shorting bar share a part for connecting each other and the part forms a common trace.
    Type: Application
    Filed: February 12, 2009
    Publication date: January 21, 2010
    Applicant: AU OPTRONICS CORPORATION
    Inventor: Jian-Hong Lin
  • Patent number: 7646207
    Abstract: A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: January 12, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hong Lin, Chin Chuan Peng, Shou-Chung Lee, Chien-Jung Wang, Chien Shih Tsai, Bi-Ling Lin, Yi-Lung Cheng
  • Publication number: 20090058434
    Abstract: A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad.
    Type: Application
    Filed: September 4, 2007
    Publication date: March 5, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Chin Chuan Peng, Shou-Chung Lee, Chien-Jung Wang, Chien Shih Tsai, Bi-Ling Lin, Yi-Lung Cheng
  • Publication number: 20080251923
    Abstract: A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.
    Type: Application
    Filed: April 10, 2007
    Publication date: October 16, 2008
    Inventors: Chien-Jung Wang, Jian-Hong Lin