Patents by Inventor Jian-Hong Lin

Jian-Hong Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070158835
    Abstract: A method is disclosed for determining a size of an interconnect between a first and a second conductor respectively in two layers of an integrated circuit while scaling from a reference processing technology to a predetermined processing technology. The method comprises selecting a set of design rules for the conductors based on the predetermined processing technology, determining a length of a first side of a rectangular cross sectional area of the interconnect based on the design rules and a scaling rule for scaling such a length from the reference processing technology to the predetermined processing technology, and determining a length of a second side of the cross sectional area of the interconnect for compensating an increase of a resistance of the interconnect due to the scaling from the reference processing technology to the predetermined processing technology.
    Type: Application
    Filed: January 12, 2006
    Publication date: July 12, 2007
    Inventors: Jian-Hong Lin, Hsueh-Chung Chen, Yi-Lung Cheng, Ta-Wei Lee, Chih-Tao Lin, Jyh-Kang Ting, Lee-Chung Lu
  • Patent number: 7235424
    Abstract: In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: June 26, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Hsueh-Chung Chen, Shin-Puu Jeng, Jian-Hong Lin, Chih-Tao Lin, Shih-Hsun Hsu
  • Publication number: 20070018279
    Abstract: A semiconductor structure prevents energy that is used to blow a fuse from causing damage. The semiconductor structure includes a device, guard ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. The seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.
    Type: Application
    Filed: July 21, 2005
    Publication date: January 25, 2007
    Inventors: Jian-Hong Lin, Kang-Cheng Lin, Tzu-Li Lee
  • Publication number: 20070015365
    Abstract: In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.
    Type: Application
    Filed: July 14, 2005
    Publication date: January 18, 2007
    Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Hsueh-Chung Chen, Shin-Puu Jeng, Jian-Hong Lin, Chih-Tao Lin, Shih-Hsun Hsu
  • Patent number: 7135406
    Abstract: Methods for forming openings in damascene structures, such as dual damascene structures are provided, using plug materials having varied etching rates. In one embodiment, a semiconductor substrate is provided with a low-k material layer formed thereabove, the low-k material layer having an upper surface and at least one via opening formed therethrough. A first plug material layer is formed over the low-k material layer and filled in the via opening, the first plug material layer having a first etching rate. The first plug material layer is etched back to form a first plug partially filling the via opening. A second plug material layer is formed over the low-k material layer and the first plug. The second plug material layer is etched back to form a second plug partially below the upper surface of the low-k material layer, the second plug material layer having a second etching rate higher than the first etching rate.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: November 14, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Hong Lin, Ying-Jen Kao, Jye-Yen Cheng
  • Publication number: 20060226507
    Abstract: A laser fuse structure for a semiconductor device, the laser fuse structure having an array of laser fuses wherein one or more of the fuses in the array have a tortuous fuse line extending between first and second connectors that connect the fuse to an underlying circuit area.
    Type: Application
    Filed: March 29, 2005
    Publication date: October 12, 2006
    Inventors: Jian-Hong Lin, Kang-Cheng Lin
  • Publication number: 20060099787
    Abstract: Methods for forming openings in damascene structures, such as dual damascene structures are provided, using plug materials having varied etching rates. In one embodiment, a semiconductor substrate is provided with a low-k material layer formed thereabove, the low-k material layer having an upper surface and at least one via opening formed therethrough. A first plug material layer is formed over the low-k material layer and filled in the via opening, the first plug material layer having a first etching rate. The first plug material layer is etched back to form a first plug partially filling the via opening. A second plug material layer is formed over the low-k material layer and the first plug. The second plug material layer is etched back to form a second plug partially below the upper surface of the low-k material layer, the second plug material layer having a second etching rate higher than the first etching rate.
    Type: Application
    Filed: November 9, 2004
    Publication date: May 11, 2006
    Inventors: Jian-Hong Lin, Ying-Jen Kao, Jye-Yen Cheng
  • Publication number: 20060040065
    Abstract: A method for surface activation on the metallization of electronic devices is provided. It uses plasma-immersion ion implantation and electroless plating to implant the seeds onto the diffusion barrier layer as catalyst for the electroless Cu plating to accomplish the ULSI interconnect metallization. It achieves electroless Cu plating in the deep 100 nm scaled line-width ULSI interconnect metallization by the Pd plasma implantation catalytic treatment. The method can fill the 100 nm line-width vias and trenches for gaining high quality electroless plated metal interconnects, and substitute for the traditional wet activation by SnCl2 and PdCl2 solution. For the plasma implanted seeds and electroless copper techniques, good Cu step coverage and gap-filling capability are observed in the trench and via metallization process with high adhesive strength. After thermal treatment, no obvious interfacial diffusion induced electric failure is found in the interface of the Cu/(implanted Pd)/TaN/FSG assembly.
    Type: Application
    Filed: August 19, 2004
    Publication date: February 23, 2006
    Inventors: Han-Chang Shih, Jian-Hong Lin, Wei-Jen Hsieh, Yi-Ying Tsai, Uei-Shin Chen