Patents by Inventor Jiang-He Xie
Jiang-He Xie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088284Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Chia-Ling YEH, Pravanshu MOHANTA, Ching-Yu CHEN, Jiang-He XIE, Yu-Shine LIN
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Publication number: 20240079486Abstract: A semiconductor structure includes a barrier layer over a channel layer, and a doped layer over the barrier layer. A gate electrode is over the doped layer and a doped interface layer is formed between the barrier layer and the doped layer. The doped interface layer includes a dopant and a metal. The metal has a metal concentration that follows a gradient function from a highest metal concentration to a lowest metal concentration.Type: ApplicationFiled: March 27, 2023Publication date: March 7, 2024Inventors: Wei-Ting CHANG, Ching Yu CHEN, Jiang-He XIE
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Patent number: 11855199Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).Type: GrantFiled: October 29, 2020Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Ling Yeh, Pravanshu Mohanta, Ching-Yu Chen, Jiang-He Xie, Yu-Shine Lin
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Patent number: 11843042Abstract: Structures and methods for controlling dopant diffusion and activation are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a channel layer; a barrier layer over the channel layer; a gate electrode over the barrier layer; and a doped layer formed between the barrier layer and the gate electrode. The doped layer includes (a) an interface layer in contact with the barrier layer and (b) a main layer between the interface layer and the gate electrode. The doped layer comprises a dopant whose doping concentration in the interface layer is lower than that in the main layer.Type: GrantFiled: August 18, 2021Date of Patent: December 12, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Yu Chen, Wei-Ting Chang, Yu-Shine Lin, Jiang-He Xie
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Publication number: 20230387282Abstract: A method of manufacturing a High-Electron-Mobility Transistor (HEMT) includes: preparing a substrate; forming a first buffer over the substrate; forming a second buffer over the first buffer, wherein forming the second buffer includes doping a first thickness of a material such as gallium nitride (GaN) with a first concentration of a dopant such as carbon, and doping a second thickness of the material with a second concentration of the dopant such that the second concentration of dopant has a gradient though the second thickness which progressively decreases in a direction away from the first thickness; forming a channel layer such as a GaN channel over the second buffer; forming a barrier layer such as aluminum gallium nitride (AlGaN) over the channel layer; and forming drain, source and gate terminals for the HEMT.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Inventors: Pravanshu Mohanta, Wei-Ting Chang, Ching Yu Chen, Jiang-He Xie
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Publication number: 20230377881Abstract: Strain relief trenches may be formed in a substrate prior to growth of an epitaxial layer on the substrate. The trenches may reduce the stresses and strains on the epitaxial layer that occur during the epitaxial growth process due to differences in material properties (e.g., lattice mismatches, differences in thermal expansion coefficients, and/or the like) between the epitaxial layer material and the substrate material. The stress and strain relief provided by the trenches may reduce or eliminate cracks and/or other types of defects in the epitaxial layer and the substrate, may reduce and/or eliminate bowing and warping of the substrate, may reduce breakage of the substrate, and/or the like. This may increase the center-to-edge quality of the epitaxial layer, may permit epitaxial layers to be grown on larger substrates, and/or the like.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Yi-Chuan LO, Pravanshu MOHANTA, Jiang-He XIE, Ching Yu CHEN, Ming-Tsung CHEN, Chia-Ling YEH
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Patent number: 11804374Abstract: Strain relief trenches may be formed in a substrate prior to growth of an epitaxial layer on the substrate. The trenches may reduce the stresses and strains on the epitaxial layer that occur during the epitaxial growth process due to differences in material properties (e.g., lattice mismatches, differences in thermal expansion coefficients, and/or the like) between the epitaxial layer material and the substrate material. The stress and strain relief provided by the trenches may reduce or eliminate cracks and/or other types of defects in the epitaxial layer and the substrate, may reduce and/or eliminate bowing and warping of the substrate, may reduce breakage of the substrate, and/or the like. This may increase the center-to-edge quality of the epitaxial layer, may permit epitaxial layers to be grown on larger substrates, and/or the like.Type: GrantFiled: October 27, 2020Date of Patent: October 31, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chuan Lo, Pravanshu Mohanta, Jiang-He Xie, Ching Yu Chen, Ming-Tsung Chen, Chia-Ling Yeh
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Patent number: 11721541Abstract: A method for forming a semiconductor arrangement is provided. The method includes forming a patterned photoresist over a top surface of a substrate. The method includes doping a first portion of the substrate using the patterned photoresist. The method includes removing the patterned photoresist using a gas comprising fluoride, wherein fluoride residue from the gas remains on the top surface of the substrate after removing the patterned photoresist. The method includes treating the substrate with nitrous oxide to remove the fluoride residue.Type: GrantFiled: March 3, 2021Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ting-Jui Chen, Chen Chih-Fen, Jason Yu, Tung-Hsi Hsieh, Jiang-He Xie
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Publication number: 20220384630Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AIN).Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Inventors: Chia-Ling YEH, Pravanshu Mohanta, Ching-Yu Chen, Jiang-He Xie, Yu-Shine Lin
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Publication number: 20220285148Abstract: A method for forming a semiconductor arrangement is provided. The method includes forming a patterned photoresist over a top surface of a substrate. The method includes doping a first portion of the substrate using the patterned photoresist. The method includes removing the patterned photoresist using a gas comprising fluoride, wherein fluoride residue from the gas remains on the top surface of the substrate after removing the patterned photoresist. The method includes treating the substrate with nitrous oxide to remove the fluoride residue.Type: ApplicationFiled: March 3, 2021Publication date: September 8, 2022Inventors: Ting-Jui CHEN, Chen CHIH-FEN, Jason YU, Tung-Hsi HSIEH, Jiang-He XIE
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Publication number: 20220140123Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).Type: ApplicationFiled: October 29, 2020Publication date: May 5, 2022Inventors: Chia-Ling YEH, Pravanshu MOHANTA, Ching-Yu CHEN, Jiang-He XIE, Yu-Shine LIN
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Publication number: 20220130670Abstract: Strain relief trenches may be formed in a substrate prior to growth of an epitaxial layer on the substrate. The trenches may reduce the stresses and strains on the epitaxial layer that occur during the epitaxial growth process due to differences in material properties (e.g., lattice mismatches, differences in thermal expansion coefficients, and/or the like) between the epitaxial layer material and the substrate material. The stress and strain relief provided by the trenches may reduce or eliminate cracks and/or other types of defects in the epitaxial layer and the substrate, may reduce and/or eliminate bowing and warping of the substrate, may reduce breakage of the substrate, and/or the like. This may increase the center-to-edge quality of the epitaxial layer, may permit epitaxial layers to be grown on larger substrates, and/or the like.Type: ApplicationFiled: October 27, 2020Publication date: April 28, 2022Inventors: Yi-Chuan LO, Pravanshu MOHANTA, Jiang-He XIE, Ching Yu CHEN, Ming-Tsung CHEN, Chia-Ling YEH
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Publication number: 20210376118Abstract: Structures and methods for controlling dopant diffusion and activation are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a channel layer; a barrier layer over the channel layer; a gate electrode over the barrier layer; and a doped layer formed between the barrier layer and the gate electrode. The doped layer includes (a) an interface layer in contact with the barrier layer and (b) a main layer between the interface layer and the gate electrode. The doped layer comprises a dopant whose doping concentration in the interface layer is lower than that in the main layer.Type: ApplicationFiled: August 18, 2021Publication date: December 2, 2021Inventors: Ching-Yu CHEN, Wei-Ting CHANG, Yu-Shine LIN, Jiang-He XIE
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Patent number: 11121230Abstract: Structures and methods for controlling dopant diffusion and activation are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a channel layer; a barrier layer over the channel layer; a gate electrode over the barrier layer; and a doped layer formed between the barrier layer and the gate electrode. The doped layer includes (a) an interface layer in contact with the barrier layer and (b) a main layer between the interface layer and the gate electrode. The doped layer comprises a dopant whose doping concentration in the interface layer is lower than that in the main layer.Type: GrantFiled: September 19, 2019Date of Patent: September 14, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Yu Chen, Wei-Ting Chang, Yu-Shine Lin, Jiang-He Xie
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Publication number: 20050133165Abstract: A chemical vapor deposition apparatus for titanium-nitride application that is useful for preventing contaminants caused by arching between a substantially planar substrate and a substrate supporting apparatus during the deposition cycle. The apparatus includes a chemical vapor deposition chamber having a substrate-supporting heater. An annular housing supported by the heater, and a conductive strap that connectively secures the substrate-supporting heater to the annular housing by using holes instead of conventional slots. The conductive strap is designed as a flexure to flex with process temperature changes to improve electrical connectivity at its terminal connection and to prevent degradation. The annular housing has a top and a bottom surface and a cylindrical wall extending peripherally below the surfaces. The cylindrical wall encircles an isolator ring.Type: ApplicationFiled: December 23, 2003Publication date: June 23, 2005Inventors: Kuang-Hsing Liu, Peter Chi, Yo-Cheng Hsueh, Jason Wu, Jiang-He Xie, Jake Chang, Wen-Hsing Liang, Hung-Cheng Chen, Kuo-Wen Chen, Feng-Shih Chiu