Abstract: A visual recognition system and a method of operation are disclosed. The visual recognition system includes: a distance sensor, configured to detect an object close to the system; and a visual recognition module, configured to compare, when the distance sensor detects the object is close, whether the object matches the preset visual recognition mode. By using a low power distance sensor in a visual recognition system, the system's power consumption can be reduced, thereby prolonging the battery lifetime of the system.

Abstract: An image sensor comprises an image sensing array on a semiconductor substrate for image sensing. The image sensor comprises a plurality of first light sensing units arranged in an array. A light sensor, disposed on the semiconductor substrates for sensing ambient light and converting the ambient light into a first electrical signal comprises a plurality of second light sensing units arranged in an array. A processing module may be connected to one or more light sensing units and may be configured to determine the intensity of the ambient light based on the first electrical signal and control the operation of the image sensor based on the determined intensity.

Abstract: An image sensor comprises an image sensing array on a semiconductor substrate for image sensing. The image sensor comprises a plurality of first light sensing units arranged in an array. A light sensor, disposed on the semiconductor substrates for sensing ambient light and converting the ambient light into a first electrical signal comprises a plurality of second light sensing units arranged in an array. A processing module may be connected to one or more light sensing units and may be configured to determine the intensity of the ambient light based on the first electrical signal and control the operation of the image sensor based on the determined intensity.

Abstract: Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with the gate electrode layer. The second surface can include silicon atoms having a concentration higher than the first surface. A sidewall spacer can be formed on the semiconductor substrate along sidewalls of each of the gate electrode layer, the silicon nitride layer, and the gate dielectric layer. The disclosed transistor can have a reduced turn-on voltage with reduced power consumption.

Abstract: Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with the gate electrode layer. The second surface can include silicon atoms having a concentration higher than the first surface. A sidewall spacer can be formed on the semiconductor substrate along sidewalls of each of the gate electrode layer, the silicon nitride layer, and the gate dielectric layer. The disclosed transistor can have a reduced turn-on voltage with reduced power consumption.

Abstract: Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with the gate electrode layer. The second surface can include silicon atoms having a concentration higher than the first surface. A sidewall spacer can be formed on the semiconductor substrate along sidewalls of each of the gate electrode layer, the silicon nitride layer, and the gate dielectric layer. The disclosed transistor can have a reduced turn-on voltage with reduced power consumption.

Abstract: Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with the gate electrode layer. The second surface can include silicon atoms having a concentration higher than the first surface. A sidewall spacer can be formed on the semiconductor substrate along sidewalls of each of the gate electrode layer, the silicon nitride layer, and the gate dielectric layer. The disclosed transistor can have a reduced turn-on voltage with reduced power consumption.

Abstract: A method for decreasing a PN junction leakage current of a dynamic random access memory (DRAM), including the steps of: preparing an NMOS transistor formed on a P-type silicon substrate and comprising a drain; forming an insulation oxide layer on the P-type silicon substrate; etching the insulation oxide layer until the P-type silicon substrate is exposed so as to form a bit line contact hole on the drain; implanting arsenic ions into the P-type silicon substrate via the bit line contact hole to form an arsenic bit line contact window; and implanting phosphorus ions into the P-type silicon substrate via the bit line contact hole to form a phosphorus bit line contact window below the arsenic bit line contact window. In this way, a concentration gradient of N-type ions can be reduced at the bit line contact window, and further a PN junction leakage current can be reduced, thus lowing the power consumption of the DRAM when the DRAM is used for a low power consumption product.

Abstract: A method for decreasing a PN junction leakage current of a dynamic random access memory (DRAM), includes the steps of: preparing an NMOS transistor formed on a P-type silicon substrate and comprising a drain; forming an insulation oxide layer on the P-type silicon substrate; etching the insulation oxide layer until the P-type silicon substrate is exposed so as to form a bit line contact hole on the drain; implanting arsenic ions into the P-type silicon substrate via the bit line contact hole to form an arsenic bit line contact window; and implanting phosphor ions into the P-type silicon substrate via the bit line contact hole to form a phosphor bit line contact window below the arsenic bit line contact window. In this way, a concentration gradient of N-type ions can be reduced at the bit line contact window, and further a PN junction leakage current can be reduced, thus lowing the power consumption of the DRAM when the DRAM is used in a low power consumption product.

Abstract: An improved design for a retaining ring for a chemical mechanical poling machine is described which provides superior flexibility and instantaneous in-situ control of the polishing rate in the edge region of a wafer. The design has a plurality of straight slurry delivery groves, angled in the direction of rotation of said ring wherein each alternate channel is recessed away from the inner circumference of the bottom, pad contacting, surface, of said retaining ring by a recess which extends upward from the bottom surface only sufficiently to prevent contact of the retaining ring with the polishing pad in the area of the recess. Each recess curves outwardly towards the inner circumference of the retaining ring in a manner to form a symmetrical segmented tab with a rounded edge, tangent to the inner circumference of the retaining ring, and meeting the inner circumference at the exit end of an adjacent non-recessed slurry channel. For a 200 mm.

Abstract: An improved design for a retaining ring for a chemical mechanical poling machine is described which provides superior flexibility and instantaneous in-situ control of the polishing rate in the edge region of a wafer. The design has a plurality of straight slurry delivery groves, angled in the direction of rotation of said ring wherein each alternate channel is recessed away from the inner circumference of the bottom, pad contacting, surface, of said retaining ring by a recess which extends upward from the bottom surface only sufficiently to prevent contact of the retaining ring with the polishing pad in the area of the recess. Each recess curves outwardly towards the inner circumference of the retaining ring in a manner to form a symmetrical segmented tab with a rounded edge, tangent to the inner circumference of the retaining ring, and meeting the inner circumference at the exit end of an adjacent non-recessed slurry channel. For a 200 mm.

Abstract: The retaining ring has a plurality of slurry channels wherein each alternate channel is recessed away from the inner circumference of the pad contacting surface forming a recess which extends upward from the bottom surface sufficient to prevent contact of the retaining ring with the polishing pad. Each recess curves towards the inner circumference of the retaining ring in a manner to form a rounded tab, tangent to the inner circumference of the retaining ring, and meeting the inner circumference at the exit end of an adjacent non-recessed slurry channel. The total effective contact length of the ring with the wafer edge is about one-tenth of the wafer perimeter. This is sufficient to properly contain the wafer during polishing and provides a large area of undistorted polishing pad at the wafer edge. By adjusting the operating pressure of the polishing head, it is possible to obtain polishing rates at the wafer edge which are larger or smaller than the overall wafer polishing rate.

Abstract: The retaining ring has a plurality of slurry channels wherein each alternate channel is recessed away from the inner circumference of the pad contacting surface forming a recess which extends upward from the bottom surface sufficient to prevent contact of the retaining ring with the polishing pad. Each recess curves towards the inner circumference of the retaining ring in a manner to form a rounded tab, tangent to the inner circumference of the retaining ring, and meeting the inner circumference at the exit end of an adjacent non-recessed slurry channel. The total effective contact length of the ring with the wafer edge is about one-tenth of the wafer perimeter. This is sufficient to properly contain the wafer during polishing and provides a large area of undistorted polishing pad at the wafer edge. By adjusting the operating pressure of the polishing head, it is possible to obtain polishing rates at the wafer edge which are larger or smaller than the overall wafer polishing rate.