Abstract: A direct memory access (DMA) controller having memory to memory data transfer capability, a programmable fixed priority scheme, a programmable wait state, a buffer chaining mode data transfer capability, a cascade-master mode, separate channels for internal and external devices, and a programmable 8 or 16 bit requester bus size. The DMA controller includes a channel circuit connected to transfer data to and from a port, a CPU interface, a bus connected to the channel circuit and to the CPU interface to transfer data therebetween, a state machine which generates a clock signal that is used for transferring data from the channel circuit across the bus to the CPU interface, the state machine having a programmable wait state which delays the transfer of data for a preprogrammed number of clock cycles, and a data mode register which is used for setting the preprogrammed number of clock cycles.

Abstract: A serial interface includes a first port capable of transmitting and receiving data in a serial fashion. A first p-channel transistor is coupled to the a first port. A first n-channel transistor is coupled to the a first port. A first control circuit is coupled to the first p-channel transistor for disabling the first p-channel transistor so that the first port can operate in a first serial data transfer mode wherein the first n-channel transistor operates in an open-drain fashion. A second port is capable of transmitting and receiving a clock signal which is used to control data transfer through the first port. A second p-channel transistor is coupled to the a second port. A second n-channel transistor is coupled to the a second port. A second control circuit is coupled to the second p-channel transistor for disabling the second p-channel transistor so that the second port can operate in the first serial data transfer mode wherein the second n-channel transistor operates in an open-drain fashion.