Patents by Inventor Jianhui Bu

Jianhui Bu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190136116
    Abstract: A low density, high-strength, degradable temporary plugging agent which includes 60% by weight to 85% by weight of polylactic acid, 5% by weight to 20% by weight of a starch, 5% by weight to 10% by weight of polycaprolactone, 2% by weight to 5% by weight of a solubilizing agent, and 2% by weight to 5% by weight of a toughening agent, based on 100% by weight of the total weight of the agent. The rigid agent can result in bridge plugging in existing cracks, with a significant increase in pressure. The preparation method is simple, the process requirements are low, and industrial production can be realized. When applied to temporary plugging fracturing, under formation conditions, it can be completely degraded within a certain period of time and will not cause secondary damage to the reservoir, while preventing the agent from polluting the formation and the occurrence of pump accidents.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Applicant: PetroChina Company Limited
    Inventors: Baoqiang LV, Lijun MU, Zhenfeng ZHAO, Hongjun LU, Xiangqian BU, Yin QI, Jianshan LI, Boping ZHAO, Xiangping LI, Jianhui LI, Li'an YANG, Jun BU
  • Patent number: 10176287
    Abstract: The invention discloses an STI stress effect modeling method and device of an MOS device, and belongs to the technical field of parameter extraction modeling of devices. The method comprises the following steps: introducing the influence of temperature parameters on the STI stress effect of the MOS device, so as to form a function showing that the STI stress effect of the MOS device changes along with the temperature parameters; extracting the model parameter Model1 of the MOS device at normal temperature; on the basis of the Model1, extracting the parameter Model2 that the STI stress affects the properties of the MOS device at normal temperature; and on the basis of the Model2, extracting fitting parameters of the MOS device in the function so as to acquire final model parameters. The device comprises a first module, a second module, a third module and a fourth module.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: January 8, 2019
    Assignee: The Institute of Microelectronics of Chinese Academy of Science
    Inventors: Jianhui Bu, Shuzhen Li, Jiajun Luo, Zhengsheng Han
  • Patent number: 9626467
    Abstract: The present invention provides a SOI MOS device modeling method. The SOI MOS device is one having a source-drain injection not reaching the bottom. The method comprises: a) establishing an overall model comprising a primary MOS device model simulating an SOI MOS device having the source-drain injection reaching the bottom, a source body PN junction bottom capacitance model simulating a source body PN junction bottom capacitance, and a drain body PN junction bottom capacitance model simulating a drain body PN junction bottom capacitance; and b) extracting parameters respectively for the primary MOS device model, the source body PN junction bottom capacitance model, and the drain body PN junction bottom capacitance model in the overall model. In the prior art, the source body junction bottom capacitance and the drain body junction bottom capacitance in the SOI MOS device having a source-drain injection not reaching the bottom affect the performances of the device.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: April 18, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Jianhui Bu, Jinshun Bi, Jiajun Luo, Zhengsheng Han
  • Publication number: 20160259876
    Abstract: The invention discloses an STI stress effect modeling method and device of an MOS device, and belongs to the technical field of parameter extraction modeling of devices. The method comprises the following steps: introducing the influence of temperature parameters on the STI stress effect of the MOS device, so as to form a function showing that the STI stress effect of the MOS device changes along with the temperature parameters; extracting the model parameter Model1 of the MOS device at normal temperature; on the basis of the Model1, extracting the parameter Model2 that the STI stress affects the properties of the MOS device at normal temperature; and on the basis of the Model2, extracting fitting parameters of the MOS device in the function so as to acquire final model parameters. The device comprises a first module, a second module, a third module and a fourth module.
    Type: Application
    Filed: April 25, 2014
    Publication date: September 8, 2016
    Inventors: Jianhui Bu, Shuzhen Li, Jiajun Luo, Zhengsheng Han
  • Publication number: 20150177312
    Abstract: The present invention provides a method for determining PN junction depth comprising: a) measuring a square resistance in a well region; b) forming a junction type field effect transistor in the well region, changing a gate electrode voltage and measuring a source-drain resistance; c) calculating the PN junction depth according to the measured square resistance, source-drain resistance and related process parameters of the junction type field effect transistor. As compared with the prior art, the technical solution in this invention determines the PN junction depth by electrical measurement, is thus simple and feasible, and has better repeatability.
    Type: Application
    Filed: September 21, 2012
    Publication date: June 25, 2015
    Inventors: Jianhui Bu, Jinshun Bi, Jiajun Luo, Zhengsheng Han
  • Publication number: 20150178429
    Abstract: The present invention provides a SOI MOS device modeling method. The SOI MOS device is one having a source-drain injection not reaching the bottom. The method comprises: a) establishing an overall model comprising a primary MOS device model simulating an SOI MOS device having the source-drain injection reaching the bottom, a source body PN junction bottom capacitance model simulating a source body PN junction bottom capacitance, and a drain body PN junction bottom capacitance model simulating a drain body PN junction bottom capacitance; and b) extracting parameters respectively for the primary MOS device model, the source body PN junction bottom capacitance model, and the drain body PN junction bottom capacitance model in the overall model. In the prior art, the source body junction bottom capacitance and the drain body junction bottom capacitance in the SOI MOS device having a source-drain injection not reaching the bottom affect the performances of the device.
    Type: Application
    Filed: September 21, 2012
    Publication date: June 25, 2015
    Inventors: Jianhui Bu, Jinshun Bi, Jiajun Luo, Zhengsheng Han