Patents by Inventor Jianmin Fang

Jianmin Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190261240
    Abstract: A handover method includes: transmitting a handover request message by a source base station to a target base station when a user equipment (UE) is being handed over from the source base station to the target base station, where the handover request message carries one or more DRB information items configured by the source base station for the UE and one or more flow QoS information items configured by a core network side for the UE; receiving, by the source base station, a handover request acknowledgement message transmitted by the target base station, where the handover request acknowledgement message carries first DRB configuration information generated by the target base station for the UE; and transmitting an RRC connection reconfiguration message carrying the first DRB configuration information by the source base station to the UE. Also disclosed is a handover apparatus.
    Type: Application
    Filed: May 2, 2019
    Publication date: August 22, 2019
    Inventors: Jianmin Fang, Xiaojuan Shi
  • Patent number: 10211183
    Abstract: A semiconductor device is made by providing a substrate, forming a first insulation layer over the substrate, forming a first conductive layer over the first insulation layer, forming a second insulation layer over the first conductive layer, and forming a second conductive layer over the second insulation layer. A portion of the second insulation layer, first conductive layer, and second conductive layer form an integrated passive device (IPD). The IPD can be an inductor, capacitor, or resistor. A plurality of conductive pillars is formed over the second conductive layer. One conductive pillar removes heat from the semiconductor device. A third insulation layer is formed over the IPD and around the plurality of conductive pillars. A shield layer is formed over the IPD, third insulation layer, and conductive pillars. The shield layer is electrically connected to the conductive pillars to shield the IPD from electromagnetic interference.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: February 19, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Patent number: 10204866
    Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: February 12, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Patent number: 10200948
    Abstract: The disclosure discloses a method and device for controlling energy saving and compensation. The method for controlling energy saving and compensation includes that: cell load measurement results of all cells in an energy saving and compensation group are acquired, the energy saving and compensation group including energy saving cells and compensation cells; and according to the cell load measurement results and an energy saving and compensation policy, at least one cell in the energy saving and compensation group are controlled to enter or quit energy saving. By means of the disclosure, energy saving and compensation can be globally controlled, thereby reducing the complexity of determining energy saving and compensation cells.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: February 5, 2019
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO., LTD.
    Inventors: Liping Chen, Weihong Zhu, Jianmin Fang
  • Patent number: 10192801
    Abstract: A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first IPD. A first semiconductor die is mounted over the substrate. An encapsulant is formed around the first conductive pillars and first semiconductor die. A second IPD is formed over the encapsulant. An interconnect structure is formed over the second IPD. The interconnect structure operates as a heat sink. A portion of a back-side of the substrate is removed to expose the first conductive via. A second semiconductor die is mounted to the back-side of the substrate. The second semiconductor die is electrically connected to the first IPD and first semiconductor die through the conductive via.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: January 29, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Patent number: 10163815
    Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: December 25, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Xia Feng, Kang Chen, Jianmin Fang
  • Patent number: 10087260
    Abstract: Disclosed are an anti-HER2 antibody and conjugate of the anti-HER2 antibody and small molecule medicine. Also disclosed are uses of the antibody and conjugate thereof in preparing medicine for treating tumor.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: October 2, 2018
    Assignee: REMEGEN, LTD.
    Inventors: Jianmin Fang, Changjiang Huang, Jing Jiang, Xuejing Yao, Hongwen Li, Qiaoyu Xu, Zhuanglin Li
  • Publication number: 20180169250
    Abstract: The present invention provides novel and advantageous compositions having a linker capable of covalently coupling one or more free thiols of an antibody. Specifically, provided herein are the molecular structures, synthetic pathways, coupling mechanisms, and applications thereof as used in an antibody-drug conjugate (ADC).
    Type: Application
    Filed: February 14, 2018
    Publication date: June 21, 2018
    Inventors: Changjiang Huang, Jianmin Fang, Hui Ye, Lezhi Zhang
  • Patent number: 9957313
    Abstract: The present invention belongs to the field of biotechnology and relates to the treatment of diseases, especially the treatment of FGF overexpression-related diseases. Particularly, the present invention relates to FGFR-Fc fusion proteins and the use thereof in the treatment of angiogenesis regulation-related diseases. More particularly, the present invention relates to isolated soluble FGFR-Fc fusion proteins and their applications in manufacture of the medicament for the treatment of angiogenesis regulation-related diseases.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: May 1, 2018
    Assignee: REMEGEN, LTD.
    Inventors: Jianmin Fang, Dong Li
  • Publication number: 20180055948
    Abstract: The present invention provides novel and advantageous compositions having a linker capable of covalently coupling one or more free thiols of an antibody. Specifically, provided herein are the molecular structures, synthetic pathways, coupling mechanisms, and applications thereof as used in an antibody-drug conjugate (ADC).
    Type: Application
    Filed: August 15, 2016
    Publication date: March 1, 2018
    Inventors: Chang Jiang HUANG, Jianmin FANG, Hui YE, Lezhi ZHANG
  • Patent number: 9865482
    Abstract: A semiconductor device is made by providing a temporary carrier for supporting the semiconductor device. An integrated passive device (IPD) is mounted to the temporary carrier using an adhesive. The IPD includes a capacitor and a resistor and has a plurality of through-silicon vias (TSVs). A discrete component is mounted to the temporary carrier using the adhesive. The discrete component includes a capacitor. The IPD and the discrete component are encapsulated using a molding compound. A first metal layer is formed over the molding compound. The first metal layer is connected to the TSVs of the IPD and forms an inductor. The temporary carrier and the adhesive are removed, and a second metal layer is formed over the IPD and the discrete component. The second metal layer interconnects the IPD and the discrete component and forms an inductor. An optional interconnect structure is formed over the second metal layer.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: January 9, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Patent number: 9754867
    Abstract: A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metallization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 ?m larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: September 5, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Publication number: 20170236788
    Abstract: A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Xia Feng, Kang Chen
  • Patent number: 9679863
    Abstract: A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: June 13, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Xia Feng, Kang Chen
  • Patent number: 9666500
    Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: May 30, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Hin Hwa Goh, Yu Gu, Il Kwon Shim, Rui Huang, Seng Guan Chow, Jianmin Fang, Xia Feng
  • Publication number: 20170148721
    Abstract: A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site.
    Type: Application
    Filed: February 8, 2017
    Publication date: May 25, 2017
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang
  • Publication number: 20170098612
    Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.
    Type: Application
    Filed: December 16, 2016
    Publication date: April 6, 2017
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Publication number: 20170084526
    Abstract: A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metallization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 ?m larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.
    Type: Application
    Filed: December 2, 2016
    Publication date: March 23, 2017
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Patent number: 9601434
    Abstract: A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: March 21, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang
  • Publication number: 20170041870
    Abstract: The disclosure discloses a method and device for controlling energy saving and compensation. The method for controlling energy saving and compensation includes that: cell load measurement results of all cells in an energy saving and compensation group are acquired, the energy saving and compensation group including energy saving cells and compensation cells; and according to the cell load measurement results and an energy saving and compensation policy, at least one cell in the energy saving and compensation group are controlled to enter or quit energy saving. By means of the disclosure, energy saving and compensation can be globally controlled, thereby reducing the complexity of determining energy saving and compensation cells.
    Type: Application
    Filed: May 29, 2014
    Publication date: February 9, 2017
    Applicant: ZTE Corporation
    Inventors: Liping CHEN, Weihong ZHU, Jianmin FANG