Patents by Inventor Jianmin Fang

Jianmin Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9558958
    Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: January 31, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Patent number: 9548240
    Abstract: A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metalization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 ?m larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: January 17, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Patent number: 9522949
    Abstract: The present invention relates to angiogenesis-inhibitory fusion proteins and use thereof. Particularly, the present invention provides fusion proteins inhibiting a plurality of angiogenic factors. More particularly, the present invention relates to the fusion proteins of VEGF receptor and FGF receptor and their applications in the treatment of angiogenesis related diseases.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 20, 2016
    Assignee: YANTAI RC BIOTECHNOLOGIES, LTD.
    Inventors: Jianmin Fang, Dong Li
  • Publication number: 20160347817
    Abstract: The present invention belongs to the field of biotechnology and relates to the treatment of diseases, especially the treatment of FGF overexpression-related diseases. Particularly, the present invention relates to FGFR-Fc fusion proteins and the use thereof in the treatment of angiogenesis regulation-related diseases. More particularly, the present invention relates to isolated soluble FGFR-Fc fusion proteins and their applications in manufacture of the medicament for the treatment of angiogenesis regulation-related diseases.
    Type: Application
    Filed: May 31, 2016
    Publication date: December 1, 2016
    Inventors: Jianmin FANG, Dong LI
  • Patent number: 9484259
    Abstract: A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: November 1, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang
  • Publication number: 20160304621
    Abstract: Disclosed are an anti-HER2 antibody and conjugate of the anti-HER2 antibody and small molecule medicine. Also disclosed are uses of the antibody and conjugate thereof in preparing medicine for treating tumor.
    Type: Application
    Filed: November 18, 2014
    Publication date: October 20, 2016
    Applicant: REMEGEN, LTD.
    Inventors: Jianmin FANG, Changjiang HUANG, Jing JIANG, Xuejing YAO, Hongwen LI, Qiaoyu XU
  • Patent number: 9472452
    Abstract: A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: October 18, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Patent number: 9449925
    Abstract: A semiconductor device has integrated passive circuit elements. A first substrate is formed on a backside of the semiconductor device. The passive circuit element is formed over the insulating layer. The passive circuit element can be an inductor, capacitor, or resistor. A passivation layer is formed over the passive circuit element. A carrier is attached to the passivation layer. The first substrate is removed. A non-silicon substrate is formed over the insulating layer on the backside of the semiconductor device. The non-silicon substrate is made with glass, molding compound, epoxy, polymer, or polymer composite. An adhesive layer is formed between the non-silicon substrate and insulating layer. A via is formed between the insulating layer and first passivation layer. The carrier is removed. An under bump metallization is formed over the passivation layer in electrical contact with the passive circuit element. A solder bump is formed on the under bump metallization.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: September 20, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Haijing Cao, Qing Zhang, Kang Chen, Jianmin Fang
  • Patent number: 9451493
    Abstract: A method, device and system for controlling assistant information of user equipment are disclosed. The field of wireless communication technology is related, and the problem is solved that the system efficiency is reduced, for UE reports the assistant information inappropriately. The method includes: the user equipment acquiring a control parameter of assistant information configured by a network side; and the user equipment reporting the assistant information of the user equipment to the network side according to the control parameter of assistant information. The technical scheme provided in the example of the present document is applied to a LTE system or a UMTS system, which implements that the network side controls the UE reporting the assistant information.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: September 20, 2016
    Assignee: ZTE Corporation
    Inventors: Dapeng Li, Lifeng Han, Zijiang Ma, He Huang, Jianmin Fang, Feng He
  • Patent number: 9437552
    Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: September 6, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng, Xusheng Bao
  • Patent number: 9401331
    Abstract: A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: July 26, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Xusheng Bao, Kang Chen, Jianmin Fang
  • Publication number: 20160197059
    Abstract: A semiconductor device is made by providing a substrate, forming a first insulation layer over the substrate, forming a first conductive layer over the first insulation layer, forming a second insulation layer over the first conductive layer, and forming a second conductive layer over the second insulation layer. A portion of the second insulation layer, first conductive layer, and second conductive layer form an integrated passive device (IPD). The IPD can be an inductor, capacitor, or resistor. A plurality of conductive pillars is formed over the second conductive layer. One conductive pillar removes heat from the semiconductor device. A third insulation layer is formed over the IPD and around the plurality of conductive pillars. A shield layer is formed over the IPD, third insulation layer, and conductive pillars. The shield layer is electrically connected to the conductive pillars to shield the IPD from electromagnetic interference.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Publication number: 20160176945
    Abstract: The present invention belongs to the field of biotechnology and relates to the treatment of diseases, especially the treatment of FGF overexpression-related diseases. Particularly, the present invention relates to FGFR-Fc fusion proteins and the use thereof in the treatment of angiogenesis regulation-related diseases. More particularly, the present invention relates to isolated soluble FGFR-Fc fusion proteins and their applications in manufacture of the medicament for the treatment of angiogenesis regulation-related diseases.
    Type: Application
    Filed: February 29, 2016
    Publication date: June 23, 2016
    Inventors: Jianmin FANG, Dong LI
  • Publication number: 20160141238
    Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.
    Type: Application
    Filed: January 27, 2016
    Publication date: May 19, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Seung Wook Yoon, Jose A. Caparas, Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Xusheng Bao, Jianmin Fang
  • Patent number: 9324700
    Abstract: A semiconductor device is made by providing a substrate, forming a first insulation layer over the substrate, forming a first conductive layer over the first insulation layer, forming a second insulation layer over the first conductive layer, and forming a second conductive layer over the second insulation layer. A portion of the second insulation layer, first conductive layer, and second conductive layer form an integrated passive device (IPD). The IPD can be an inductor, capacitor, or resistor. A plurality of conductive pillars is formed over the second conductive layer. One conductive pillar removes heat from the semiconductor device. A third insulation layer is formed over the IPD and around the plurality of conductive pillars. A shield layer is formed over the IPD, third insulation layer, and conductive pillars. The shield layer is electrically connected to the conductive pillars to shield the IPD from electromagnetic interference.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: April 26, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Patent number: 9293401
    Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: March 22, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Seung Wook Yoon, Jose A. Caparas, Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Xusheng Bao, Jianmin Fang
  • Patent number: 9273137
    Abstract: The present invention belongs to the field of biotechnology and relates to the treatment of diseases, especially the treatment of FGF overexpression-related diseases. Particularly, the present invention relates to FGFR-Fc fusion proteins and the use thereof in the treatment of angiogenesis regulation-related diseases. More particularly, the present invention relates to isolated soluble FGFR-Fc fusion proteins and their applications in manufacture of the medicament for the treatment of angiogenesis regulation-related diseases.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 1, 2016
    Assignee: REMEGEN, LTD.
    Inventors: Jianmin Fang, Dong Li
  • Patent number: 9269598
    Abstract: A semiconductor device has a first conductive layer formed over a sacrificial substrate. A first integrated passive device (IPD) is formed in a first region over the first conductive layer. A conductive pillar is formed over the first conductive layer. A high-resistivity encapsulant greater than 1.0 kohm-cm is formed over the first IPD to a top surface of the conductive pillar. A second IPD is formed over the encapsulant. The first encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs. An insulating layer is formed over the second IPD. The sacrificial substrate is removed and a second semiconductor die is disposed on the first conductive layer. A first semiconductor die is formed in a second region over the substrate. A second encapsulant is formed over the second semiconductor die and a thermally conductive layer is formed over the second encapsulant.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: February 23, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Patent number: 9252075
    Abstract: A semiconductor device is made from a semiconductor wafer containing semiconductor die separated by a peripheral region. A conductive via-in-via structure is formed in the peripheral region or through an active region of the device to provide additional tensile strength. The conductive via-in-via structure includes an inner conductive via and outer conductive via separated by insulating material. A middle conductive via can be formed between the inner and outer conductive vias. The inner conductive via has a first cross-sectional area adjacent to a first surface of the semiconductor device and a second cross-sectional area adjacent to a second surface of the semiconductor device. The outer conductive via has a first cross-sectional area adjacent to the first surface of the semiconductor device and a second cross-sectional area adjacent to the second surface of the semiconductor device. The first cross-sectional area is different from the second cross-sectional area.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: February 2, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Lionel Chien Hui Tay, Jianmin Fang, Zigmund R. Camacho
  • Patent number: 9202713
    Abstract: A semiconductor device has a semiconductor die with an active surface. A first conductive layer is formed over the active surface. A first insulating layer is formed over the active surface. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second insulating layer is removed over the first conductive layer so that no portion of the second insulating layer overlies the first conductive layer. A second conductive layer is formed over the first conductive layer and first and second insulating layers. The second conductive layer extends over the first conductive layer up to the first insulating layer. Alternatively, the second conductive layer extends across the first conductive layer up to the first insulating layer on opposite sides of the first conductive layer. A third insulating layer is formed over the second conductive layer and first and second insulating layers.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: December 1, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng