Patents by Inventor Jianmin Fang

Jianmin Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9184103
    Abstract: A semiconductor device includes a first conductive layer and conductive pillars disposed over the first conductive layer and directly contacting the first conductive layer. The semiconductor device includes an Integrated Passive Device (IPD) mounted to the first conductive layer such that the IPD is disposed between the conductive pillars. The IPD is self-aligned to the first conductive layer, and includes a metal-insulator-metal capacitor disposed over a first substrate and a wound conductive layer forming an inductor disposed over the first substrate. The semiconductor device includes a discrete capacitor mounted over the first conductive layer. The discrete capacitor is electrically connected to one of the conductive pillars. The semiconductor device includes an encapsulant disposed around the IPD, discrete capacitor, and conductive pillars, a first insulation layer disposed over the encapsulant and conductive pillars, and a second conductive layer disposed over the first insulating layer.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: November 10, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Haijing Cao, Kang Chen, Jianmin Fang
  • Publication number: 20150228552
    Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
    Type: Application
    Filed: April 27, 2015
    Publication date: August 13, 2015
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Hin Hwa Goh, Yu Gu, Il Kwon Shim, Rui Huang, Seng Guan Chow, Jianmin Fang, Xia Feng
  • Patent number: 9087930
    Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: July 21, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Hin Hwa Goh, Yu Gu, Il Kwon Shim, Rui Huang, Seng Guan Chow, Jianmin Fang, Xia Feng
  • Patent number: 9082832
    Abstract: A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: July 14, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang
  • Publication number: 20150155248
    Abstract: A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metalization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 ?m larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.
    Type: Application
    Filed: February 9, 2015
    Publication date: June 4, 2015
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Patent number: 9019881
    Abstract: A method for waking up a Node B (NB) cell is provided. When a User Equipment (UE) in an idle state arrives in an area of a Home NB cell in which the UE ever resided, but does not search out signals of the Home cell, the UE reports Proximity Indication (PI) information to a network side through a specific Tracking Area Update (TAU) process; when determining that there is need to wake up the NB cell according to footprint information which is reported by the UE and obtained in the specific TAU process, the network side wakes up the NB cell. The method ensures that the UE in an idle state wakes up the sleeping Home NB cell (or macro cell) in time and gets service from the Home NB cell (or macro cell), thus a network coverage problem caused by cell sleeping for saving energy is avoided.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: April 28, 2015
    Assignee: ZTE Corporation
    Inventors: Jianmin Fang, Lifeng Han, Yin Gao
  • Publication number: 20150102816
    Abstract: An apparatus and method for identifying batteries with different thickness, and an electronic device thereof, the apparatus comprises a buckle switch arranged at a position close to battery compartment in the electronic device, and a control circuit connected with the buckle switch. When a thin battery is mounted in the electronic device, the state of the buckle switch is ON; and when a thick battery is mounted in the electronic device, the state of the buckle switch is OFF. According to the ON/OFF state of the buckle switch, the control circuit identifies whether a thin battery or a thick battery is mounted in the electronic device. The apparatus and method can identify whether a thin battery or a thick battery is used in the electronic device, and thereby can adopt different drivers to manage the battery.
    Type: Application
    Filed: June 29, 2012
    Publication date: April 16, 2015
    Applicant: ZTE CORPORATION
    Inventors: Kai Ma, Jianmin Fang
  • Publication number: 20150092579
    Abstract: A method, device and system for controlling assistant information of user equipment are disclosed. The field of wireless communication technology is related, and the problem is solved that the system efficiency is reduced, for UE reports the assistant information inappropriately. The method includes: the user equipment acquiring a control parameter of assistant information configured by a network side; and the user equipment reporting the assistant information of the user equipment to the network side according to the control parameter of assistant information. The technical scheme provided in the example of the present document is applied to a LTE system or a UMTS system, which implements that the network side controls the UE reporting the assistant information.
    Type: Application
    Filed: March 27, 2013
    Publication date: April 2, 2015
    Inventors: Dapeng Li, Lifeng Han, Zijiang Ma, He Huang, Jianmin Fang, Feng He
  • Patent number: 8977325
    Abstract: The present invention provides a method and a system for processing cell sleeping. The method comprises: a cell sending a sleeping request message to a neighbor cell (S102); according to the sleeping request message, the neighbor cell sends a corresponding sleeping response message to the cell (S104); according to the sleeping response message, the cell decides to perform sleeping or not (S106). The present invention ensures the continuity of user communication.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: March 10, 2015
    Assignee: ZTE Corporation
    Inventors: Jianmin Fang, Feng He, Yin Gao
  • Publication number: 20150008597
    Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.
    Type: Application
    Filed: September 23, 2014
    Publication date: January 8, 2015
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Patent number: 8907476
    Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: December 9, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Publication number: 20140339683
    Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.
    Type: Application
    Filed: August 1, 2014
    Publication date: November 20, 2014
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng, Xusheng Bao
  • Patent number: 8878359
    Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: November 4, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng, Xusheng Bao
  • Patent number: 8843172
    Abstract: A method for determining an initial transmission power and a base station is provided. The method comprises: a base station acquiring a measurement result of a second cell reported by said user equipment, wherein a first cell in which a user equipment (UE) is located belongs to the base station, and said first cell and said second cell belong to different base stations; and determining an initial transmission power of said user equipment when initiating a random access in said second cell according to a reference signal power of said second cell, said measurement result and a random access initial received target power of said second cell. Success rate of handover of user equipment is improved.
    Type: Grant
    Filed: May 31, 2010
    Date of Patent: September 23, 2014
    Assignee: ZTE Corporation
    Inventors: Feng He, Jianmin Fang
  • Publication number: 20140252654
    Abstract: A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer.
    Type: Application
    Filed: May 22, 2014
    Publication date: September 11, 2014
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Publication number: 20140246779
    Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
    Type: Application
    Filed: May 9, 2014
    Publication date: September 4, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Hin Hwa Goh, Yu Gu, Il Kwon Shim, Rui Huang, Seng Guan Chow, Jianmin Fang, Xia Feng
  • Publication number: 20140239495
    Abstract: A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.
    Type: Application
    Filed: May 1, 2014
    Publication date: August 28, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Xusheng Bao, Kang Chen, Jianmin Fang
  • Patent number: 8796846
    Abstract: A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: August 5, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Xusheng Bao, Kang Chen, Jianmin Fang
  • Patent number: 8786100
    Abstract: A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: July 22, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng
  • Patent number: 8759155
    Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: June 24, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Hin Hwa Goh, Yu Gu, Il Kwon Shim, Rui Huang, Seng Guan Chow, Jianmin Fang, Xia Feng