Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.

Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.

Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.

Abstract: A method for determining an initial transmission power and a base station is provided. The method comprises: a base station acquiring a measurement result of a second cell reported by said user equipment, wherein a first cell in which a user equipment (UE) is located belongs to the base station, and said first cell and said second cell belong to different base stations; and determining an initial transmission power of said user equipment when initiating a random access in said second cell according to a reference signal power of said second cell, said measurement result and a random access initial received target power of said second cell. Success rate of handover of user equipment is improved.

Abstract: A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer.

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract: A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.

Abstract: A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.

Abstract: A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer.

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die.

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die.

Abstract: A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A conductive material is deposited in the TSV in electrical contact with the analog circuit. An under bump metallization layer is formed on a backside of the substrate in electrical contact with the TSV. A solder material is deposited on the UBM layer. The solder material is reflowed to form a solder bump. A wire bond is formed on a top surface of the substrate. A redistribution layer is formed between the TSV and UBM. The analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate.

Abstract: A semiconductor wafer has a first conductive layer formed over its active surface. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A UBM layer is formed around a bump formation area over the second conductive layer. The UBM layer can be two stacked metal layers or three stacked metal layers. The second conductive layer is exposed in the bump formation area. A second insulating layer is formed over the UBM layer and second conductive layer. A portion of the second insulating layer is removed over the bump formation area and a portion of the UBM layer. A bump is formed over the second conductive layer in the bump formation area. The bump contacts the UBM layer to seal a contact interface between the bump and second conductive layer.

Abstract: A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Abstract: The disclosure discloses a method for mobility parameter negotiation between base stations (BSs). A target BS performs a mobility parameter decision and an optimization processing after receiving a mobility parameter modification request message from a source BS. When the processing succeeds, the target BS sends a mobility parameter modification acknowledgement message at least carrying a message type and a source cell ID to the source BS; when it fails, the target BS sends a mobility parameter modification failure message at least carrying a message type, a reason of failure, and the source cell ID to the source BS. A system for mobility parameter negotiation between BSs is also provided.

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract: A semiconductor device includes an IPD structure, a first semiconductor die mounted to the IPD structure with a flipchip interconnect, and a plurality of first conductive posts that are disposed adjacent to the first semiconductor die. The semiconductor device further includes a first molding compound that is disposed over the first conductive posts and first semiconductor die, a core structure bonded to the first conductive posts over the first semiconductor die, and a plurality of conductive TSVs disposed in the core structure. The semiconductor device further includes a plurality of second conductive posts that are disposed over the core structure, a second semiconductor die mounted over the core structure, and a second molding compound disposed over the second conductive posts and the second semiconductor die. The second semiconductor die is electrically connected to the core structure.

Abstract: A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.